TMP86PM74AFG datasheet(53/190 Pages) TOSHIBA

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Page 43

TMP86PM74AFG

3.6

Undefined Instruction Interrupt (INTUNDEF)

Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is gen-

erated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable inter-

rupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is

requested.

Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt

(SWI) does.

3.7

Address Trap Interrupt (INTATRAP)

Fetching instruction from unauthorized area for instructions (Address trapped area) causes reset output or address

trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contemporary pro-

cess is broken and INTATRAP interrupt process starts, soon after it is requested.

Note: The operating mode under address trapped, whether to be reset output or interrupt processing, is selected on

watchdog timer control register (WDTCR).

3.8

External Interrupts

The TMP86PM74AFG has 6 external interrupt inputs. These inputs are equipped with digital noise reject circuits

(Pulse inputs of less than a certain time are eliminated as noise).

Edge selection is also possible with INT1 to INT4. The INT0/P50 pin can be configured as either an external inter-

rupt input pin or an input/output port, and is configured as an input port during reset.

Edge selection, noise reject control and INT0/P50 pin function selection are performed by the external interrupt

control register (EINTCR).

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