TMP93CS44 datasheet(30/224 Pages) TOSHIBA

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TMP93CS44/S45

2004-02-10

93CS44-28

4. STOP mode

The STOP mode is selected to stop all internal circuits including the internal

oscillator. The pin status in the STOP mode depends on setting of a bit in the

watchdog timer mode register WDMOD<DRVE>. (See Figure 3.3.5 for setting of

WDMOD<DRVE>.) Table 3.3.7 summarizes the state of these pins in the STOP

mode.

The STOP mode is released by external interrupts (NMI, INT0). When the

STOP mode is released, the system clock output starts after warm-up time

required to attain stable oscillation. The warm-up time can be set using

WDMOD<WARM>. See the example of warm-up time (Table 3.3.6).

In a system which supplies stable clock generated by an external oscillator, the

warm-up time can be reduced by using the setting of T45CR<QCU>.

Figure 3.3.8 illustrates the timing for releasing the halt state by interrupts

during the STOP mode.

Figure 3.3.8 Timing Chart of Halt State Release by Interrupts in STOP Mode

Address

Data

Address

Data

STOP

mode

CLK

A0 to A23

ALE

AD0 to AD15

NMI

INT0

(Level)

INT0

(Rising edge)

Warm-up

time

Address

+ 2

Address

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