TMP93CS44 datasheet(100/224 Pages) TOSHIBA

100 / 224 page

TMP93CS44/S45

2004-02-10

93CS44-98

In this mode, the value of register buffer will be shifted in TREG2 if 2n

− 1 overflow is

detected when the double buffer of TREG2 is enabled.

Use of the double buffer makes easy the handling of small duty waves.

Figure 3.7.18 Operation of Register Buffer

Example: To output the following PWM waves to TO3 pin at fc

= 20 MHz.

* Clock condition

System clock:

High frequency (fs)

Clock gear:

1 (fc)

Prescaler clock: fFPH

To realize 50.8

µs of PWM cycle by φT1 = 0.4 µs (at fc = 20 MHz),

50.8

µs ÷ 0.4 µs = 127 = 2n − 1

Consequently, n should be set to 7.

As the period of low level is 28.8

µs, for φT1 = 0.4 µs,

set the following value for TREG2.

28.8

µs ÷ 0.4 µs = 72 = 48H

MSB

LSB

TRUN

← − X − − − 0 − −

Stop timer 2, and clear it to “0”.

T32MOD

← 1 1 1 0 − − 01

Set 8-bit PWM mode (cycle: 2

− 1) and select φT1 as the

input clock.

TREG2

← 0 1 0 0 1 0 0 0

Writes “48H”.

TFFCR

← 1 0 1 X − − − −

Clears TFF3, enable the inversion and double buffer.

P4CR

← − − − − − − 1 −

P4FC

← − X X − X X 1 X

Set P41 as the TO3 pin.

TRUN

← 1 X − − − 1 − −

Start timer 2 counting.

X: Don’t care,

−: No change

Match with TREG2

Up counter

= Q1

Up counter

= Q2

Shift into TREG2

TREG2 (Register buffer)

write

TREG2

(Value to be compared)

− 1 overflow

28.8

µs

50.8

µs

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