TMP93CS44 datasheet(60/224 Pages) TOSHIBA

60 / 224 page

TMP93CS44/S45

2004-02-10

93CS44-58

3.5.4

Port 3 (P30 to P35)

Port 3 is an 6-bit general-purpose I/O port.

I/O can be set on a bit basis, but note that P30 and P31 are used for output only. I/O is set

using control register P3CR and function register P3FC. Resetting sets all bits of output

latch P3 to 1. All bits of control register P3CR (bits 0 and 1 are unused), and function

In addition to functioning as a general-purpose I/O port, port 3 also shares functions as

an I/O for the CPU’s control/status signal and serial bus interface.

With the TMP93CS44, when P30 pin is defined as RD signal output mode (<P30F>

= 1),

setting the output latch register <P30> to 0 outputs the RD strobe (Used for the pseudo

static RAM) from the P30 pin even when the internal address area is accessed.

If the output latch register <P30> remains 1, the RD strobe signal is output only when

the external address area is accessed.

When P33 and P34 are used as the serial bus interface I/O pins in I2C bus mode

(P3FC<P34F:P33F>

= 11), set open drain outputs (ODE<ODE34:33> = 11).

With the TMP93CS45, which needs external ROMs, P30 outputs the RD signal; P31, the

signal, regardless of the values set in function registers <P30F> and <P31F>.

The RD signal is output not only when the external address area is accessed at <P30>

1 but also the internal address area is accessed at <P30>

= 0.

TMP93CS44 bảng dữ liệu(PDF) 60 Page - Toshiba Semiconductor