TMP93CS44 datasheet(88/224 Pages) TOSHIBA

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TMP93CS44/S45

2004-02-10

93CS44-86

4. Comparator

A comparator compares the value in the up counter with the values to which the

timer register is set. When they match, the up counter is cleared to zero and an

interrupt signal (INTT0, INTT1, INTT2, INTT3) is generated. If the timer flip-flop

inversion is enabled, the timer flip-flop is inverted at the same time.

5. Timer flip-flop (Timer F/F: TFF1, TFF3)

The timer flip-flop is a flip-flop inverted by the match detect signal (8-bit comparator

output) of each interval timer.

Inverting is disabled or enabled by the timer flip-flop control register

TFFCR<TFF3IE, TFF1IE>.

After reset operation, the value of TFF1, TFF3 is undefined. Writing 01 or 10 to

TFFCR<TFF3C1:0, TFF1C1:0> sets 0 or 1 to TFF1, TFF3. Additionally, writing 00 to

this bit inverts the value of TFF1, TFF3. (Software inversion.)

The signal of TFF3 is output through the TO3 pin (Also used as P41). When using as

the timer output, the timer flip-flop should be set by port 4 function register P4FC

beforehand. The output pin of TFF1 does not exist.

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