TMP93CS44 datasheet(190/224 Pages) TOSHIBA

190 / 224 page

TMP93CS44/S45

2004-02-10

93CS44-188

3.12.3

Operation

The watchdog timer generates interrupt INTWD after the detecting time set in the

WDMOD<WDTP1:0>. The watchdog timer must be zero cleared by software before an

INTWD interrupt is generated. If the CPU malfunctions (Runaway) due to causes such as

noise, but does not execute the instruction used to clear the binary counter, the binary

counter overflows and an INTWD interrupt is generated. The CPU detects malfunction

(Runaway) due to the INTWD interrupt and it is possible to return to normal operation by

an anti-malfunction program. By connecting the watchdog timer out pin to peripheral

devices’ resets, a CPU malfunction can also be acknowledged to other devices.

The watchdog timer restarts operation immediately after resetting is released.

The watchdog timer stops its operation in the IDLE1 and STOP modes. In the RUN mode,

the watchdog timer is enabled.

However, the function can be disabled when entering the RUN, IDLE2 mode.

Example:

1. Clear the binary counter

WDCR

← 0 1 0 0 1 1 1 0

Write clear code (4EH).

2. Set the watchdog timer detecting time to 217/fSYS

WDMOD

← 1 0 1 −− − XX

3. Disable the watchdog timer

WDMOD

← 0 − − − − − X X

Clear WDTE to 0.

WDCR

← 1 0 1 1 0 0 0 1

Write disable code (B1H).

4. Set IDLE1 mode

WDMOD

← 0 − − − 1 0 XX

WDCR

← 1 0 1 1 0 0 0 1

Disables WDT and sets IDLE1 mode.

Executes halt command

Set the HALT mode.

5. Set the STOP mode (Warm-up time: 216/fSYS)

WDMOD

← − − − 1 0 1 X X

Set the STOP mode.

Executes halt command

Execute HALT instruction. Set the HALT

mode.

X: Don’t care,

−: No change

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