TMP93CS44 datasheet(163/224 Pages) TOSHIBA

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TMP93CS44/S45

2004-02-10

93CS44-161

In order to terminate the transmitting data to the transmitter, set <ACK> to 0

before reading data which is 1 word before the last data to be received. The last

data does not generate a clock pulse for the acknowledge signal. After the data is

transmitted and an interrupt request has occurred, set <BC2:0> to 001 and read

the data. The TMP93CS44/S45 generates a clock pulse for a 1-bit data transfer.

Since the master device is a receiver, the SDA line of the bus keeps the high level.

The transmitter receives the high-level signal as the ACK signal. The receiver

indicates to the transmitter that data transfer is complete.

After 1-bit data is received and the interrupt request has occurred, the

TMP93CS44/S45 generates the stop condition and terminates data transfer.

Figure 3.10.15 Termination of Data Transfer in Master Receiver Mode

456781

Acknowledge signal

sent to a transmitter

SCL pin

SDA pin

<PIN>

INTS2

interrupt request

"001"

→ <BC2:0>

Read SBIDBR

“0”

→ <ACK> Read SBIDBR

Output of master

Output of slave

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