TMP93CS44 datasheet(147/224 Pages) TOSHIBA

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TMP93CS44/S45

2004-02-10

93CS44-145

Protocol

1. Select the 9-bit UART mode for the master and slave controllers.

2. Set SC0MOD<WU> bit of each slave controller to 1 to enable data receiving.

3. The master controller transmits one-frame data including the 8-bit select code for

the slave controllers. The MSB (Bit8) <TB8> is set to 1.

4. Each slave controller receives the above frame, and clears <WU> bit to 0 if the

above select code matches its own select code.

5. The master controller transmits data to the specified slave controller whose

SC0MOD<WU> bit is cleared to 0. The MSB (Bit8) <TB8> is cleared to 0.

6. The other slave controllers (with the <WU> bit remaining at 1) ignore the

receiving data because their MSBs (Bit8 or <RB8>) are set to 0 to disable the

interrupt INTRX0.

The slave controllers (<WU>

= 0) can transmit data to the master controller, and

it is possible to indicate the end of data receiving to the master controller by this

transmission.

Start

Bit0

123

456

Select code of slave controller

Stop

“1”

Start

Bit0

123

456

Data

Stop

Bit8

“0”

TMP93CS44 bảng dữ liệu(PDF) 147 Page - Toshiba Semiconductor