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TMP93CS32F bảng dữ liệu(PDF) 120 Page - Toshiba Semiconductor |
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TMP93CS32F bảng dữ liệu(HTML) 120 Page - Toshiba Semiconductor |
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120 / 180 page ![]() TMP93CS32 2004-02-10 93CS32-118 Serial channel 0 and 1 can be used independently. All serial channels operate in the same manner, and thus only operation of serial channel 0 will be explained below. 1. Prescaler There are 9-bit prescaler and prescaler clock selection registers to generate input clock for 8-bit timers 0, 1, 2, 3 and 16-bits timers 4, 5 and Serial interface 0, 1. Figure 3.9.11 shows the block diagram. Table 3.9.1 shows prescaler clock resolution into the baud rate generator. Figure 3.9.11 The Block Diagram of Prescaler Table 3.9.1 Prescaler Clock Resolution to Baud Rate Generator at fc = 20 MHz Prescaler Output Clock Resolution Select Prescaler Clock <PRCK1:0> Gear value <GEAR2:0> φT0 φT2 φT8 φT32 000 (fc) fc/2 2 (0.2 µs) fc/2 4 (0.8 µs) fc/2 6 (3.2 µs) fc/2 8 (12.8 µs) 001 (fc/2) fc/2 3 (0.4 µs) fc/2 5 (1.6 µs) fc/2 7 (6.4 µs) fc/2 9 (25.6 µs) 010 (fc/4) fc/2 4 (0.8 µs) fc/2 6 (3.2 µs) fc/2 8 (12.8 µs) fc/2 10 (51.2 µs) 011 (fc/8) fc/2 5 (1.6 µs) fc/2 7 (6.4 µs) fc/2 9 (25.6 µs) fc/2 11 (102.4 µs) 00 (fFPH) 100 (fc/16) fc/2 6 (3.2 µs) fc/2 8 (12.8 µs) fc/2 10 (51.2 µs) fc/2 12 (204.8 µs) 10 (fc/16 clock) XXX − fc/2 8 (12.8 µs) fc/2 10 (51.2 µs) fc/2 12 (204.8 µs) XXX: Don’t care −: Can not use 512 256 128 64 32 16 8 4 2 φT1 φT4 φT16 φT256 φT1 φT4 φT16 φ1 φT0 φT2 φT8 φT32 ÷2 ÷2 ÷4 ÷16 ÷8 ÷4 ÷2 To CPU System clock (fSYS) 9-bit Prescaler To 8-bit timers 0, 1, 2, and 3 X1 fc/16 fc/8 fc/4 fc/2 fc SYSCR1<GEAR2:0> TRUN<PRRUN> SYSCR0 <PRCK1:0> Run/Stop & clear To 16-bit timers 4 and 5 To serial interfaces 0 and 1 fFPH |
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