TMP93CS32F datasheet(72/180 Pages) TOSHIBA

72 / 180 page

TMP93CS32

2004-02-10

93CS32-70

(

3) Timer register

This is an 8-bit register for setting an interval time. When the set value of timer registers

TREG0, TREG1, TREG2, and TREG3, matches the value of up-counter, the comparator

match detect signal becomes active. If the set value is 00H, this signal becomes active when

the up-counter overflows.

Timer registers TREG2, are double buffer structure, each of which makes a pair with

The timer flip-flop controll register TRDC<TR2DE> bits control whether the double

buffer structure in the TREG2 should be enabled or disabled. They are disabled when

<TR2DE>

= 0 and enabled when they are set to 1.

In the condition of double buffer enable state, the data is transfered from the register

buffer to the timer register when the 2n

− 1 overflow occurs in PWM mode, or at the PPG

cycle in PPG mode. Therefore, during timer mode, the double buffer can not be used.

When reset, it will be initialized to <TR2DE>

= 0 to disable the double buffer. To use the

double buffer, write data in the timer register, set <TR2DE> to 1, and write the following

data in the register buffer.

Figure 3.7.4 Configuration of Timer Register 2

Note:

Timer register and the register buffer are allocated to the same memory address.

When <TR2DE> = 0, the same value is written in the register buffer as well as the

timer register, while when <TR2DE> = 1 only the register buffer is written.

The memory address of each timer register is as follows.

TREG0 : 000022H

TREG2 : 000026H

TREG1 : 000023H

TREG3 : 000027H

All the registers are write-only and cannot be read.

Comparator (CP2)

Internal data bus

TRDC<TR2DE>

Timer registers 2 (TREG2)

Shift trigger

Selector

Write

TREG2 WR

Matching detection of PPG cycle

− 1 overflow of PWM

Up counter

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