TMP93CS32F datasheet(27/180 Pages) TOSHIBA

27 / 180 page

TMP93CS32

2004-02-10

93CS32-25

3.4.1

General-Purpose Interrupt Processing

When accepting an interrupt, the CPU operates as follows. In the cases of software

interrupts or interrupts generated by the CPU because of attempts to execute illegal

instructions, the following steps (1) and (3) are not executed.

(1) The CPU reads the interrupt vector from the interrupt controller. When more than one

interrupt with the same level is generated simultaneously, the interrupt controller

generates interrupt vectors in accordance with the default priority (which is fixed as

follows: the smaller the vector value, the higher the priority), then clears the interrupt

request.

(2) The CPU pushes the program counter and the status register to the system stack area

(Area indicated by the system mode stack pointer (XSP)).

(3) The CPU sets a value in the CPU interrupt mask register <IFF2:0> that is higher by 1

than the value of the accepted interrupt level. However, if the value is 7, 7 is set

without an increment.

(4) The CPU increments the INTNEST (Interrupt nesting counter).

(5) The CPU jumps to address stored at FFFF00H

+ interrupt vector, then starts the

interrupt processing routine.

The following diagram shows all the above processing state number.

Bus Width of

Stack Area

Bus Width of

Interrupt

Vector Area

Interrupt Processing State

Number

8 bits

16 bits

8 bits

16 bits

To return to the main routine after completion of the interrupt processing, the “RETI”

instruction is usually used. Executing this instruction restores the contents of the program

counter and the status registers and decrements INTNEST (Interrupt nesting counter).

Though acceptance of non-maskable interrupts cannot be disabled by program,

acceptance of maskable interrupts can. A priority can be set for each source of maskable

interrupts. The CPU accepts an interrupt request with a priority higher than the value in

the CPU mask register <IFF2:0>. The CPU mask register <IFF2:0> is set to a value higher

by 1 than the priority of the accepted interrupt. Thus, if an interrupt with a level higher

than the interrupt being processed is generated, the CPU accepts the interrupt with the

higher level, causing interrupt processing to nest.

The interrupt request with a priority higher than the accepted now interrupt during the

CPU is processing above (1) to (5) is accepted before the 1’st instruction in the interrupt

processing routine, causing interrupt processing to nest. (This is the same case of over

lapped each Non-maskable interrupt (level 7).) (Non-maskable interrupts (level 7) can be

accepted, causing interrupt processing to rest.)

The CPU does not accept an interrupt request of the same level as that of the interrupt

being processed.

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