TMPR4938 datasheet(191/716 Pages) TOSHIBA

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Chapter 8 DMA Controller

8-17

8.3.9

DMA Transfer

The sequence of DMA transfer that uses only the DMA Channel Register is as follows below.

Select DMA request signal

When performing external I/O or internal I/O DMA, set the DMA Request Select field

(PCFG.DMASEL) of the Pin Configuration Register.

Set the Master Enable bit

Set the Master Enable bit (DMMCR.MSTEN) of the DMA Master Control Register.

Set the Address Register and Count Register

Set the five following register values.

•

DMA Source Address Register (DMSARn)

•

DMA Destination Address Register (DMDARn)

•

DMA Count Register (DMCNTRn)

•

DMA Source Address Increment Register (DMSAIRn)

•

DMA Destination Address Increment Register (DMDAIRn)

Set Chain Address Register

Set “0” to the DMA Chain Address Register (DMCHARn).

Clear the DMA Channel Status Register (DMCSRn)

Clear when status from the previous DMA transfer remains.

Set the DMA Channel Control Register (DMCCRn)

Initiate DMA transfer

DMA transfer is started by setting the Transfer Active bit (XFACT) of the DMA Channel Control

Signal completion

When DMA data transfer ends normally, set the Normal Transfer Complete bit (NTRNFC) of the

DMA Channel Status Register (DMCSRn). An interrupt is signalled if the Transfer Complete

Interrupt Enable bit (INTENT) of the DMA Channel Control Register (DMCCRn) is set.

If an error is detected during DMA transfer, the error cause is recorded in the lower four bits of the

DMA Channel Status Register and the transfer is interrupted. If the Error Interrupt Enable bit

(INTENE) of the DMA Channel Control Register is set, then the interrupt is signaled.

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