TMPR4938 datasheet(64/716 Pages) TOSHIBA

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Chapter 3 Signals

3-10

3.1.15 NAND Flash Memory Interface Signals

Table 3.1.15 NAND Flash Memory Interface Signals

Signal Name

Type

Description

Initial State

ND_ALE

Output

NAND Flash Address Latch Enable

ALE signal for NAND flash memory. These signals are common with the other functions

(refer to Section “3.3 Pin Multiplex”). Use the configuration setting during boot-up.

Input

ND_CLE

Output

NAND Flash Command Latch Enable

CLE signal for NAND flash memory. These signals are common with the other functions

(refer to Section “3.3 Pin Multiplex”). Use the configuration setting during boot-up.

High

ND_CE*

Output

NAND Flash Chip Enable

CE signal for NAND flash memory. Refer to Section “3.3 Pin multiplex”

High

ND_RE*

Output

NAND Flash Read Enable

RE signal for NAND flash memory. These signals are common with the other functions

(refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up.

Input

ND_WE*

Output

NADND Flash Write Enable

WE signal for NAND flash memory. These signals are common with the other functions

(refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up.

High

ND_RB*

Input

NAND Flash Ready/Busy

Ready/Busy signal for NAND flash memory. These signals are common with the other

functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-

up.

Input

3.1.16 Extended EJTAG Interface Signals

Table 3.1.16 Extended EJTAG Interface Signals (1/2)

Signal Name

Type

Description

Initial State

TCK

Input

JTAG Test Clock Input

Clock input signal for JTAG.

TCK is used to execute JTAG instructions and input/output data.

Input

TDI/DINT*

Input

JTAG Test Data Input/Debug Interrupt

When PC trace mode is not selected, this signal is a JTAG data input signal. It is used to

input serial data to JTAG data/instruction registers.

When PC trace mode is selected, this signal is an interrupt input signal used to cancel

PC trace mode for the debug unit.

Input

TDO/TPC[0]

Output

JTAG Test Data Output/PC Trace Output

When PC trace mode is not selected, this signal is a JTAG data output signal. Data is

output by means of serial scan.

When PC trace mode is selected, this signal outputs the value of the non-continuous

program counter in sync with the debug clock (DCLK).

High

TPC[3:1]

Output

PC Trace Output

TPC[3:1] output the value of the noncontiguous program counter in sync with DCLK.

These signals are common with the other functions (refer to Section “3.3 Pin multiplex”).

Use the configuration setting during boot-up.

All High

TMS

Input

JTAG Test Mode Select Input

TMS mainly controls state transition in the TAP controller state machine.

Input

TRST*

Input

Test Reset Input

Asynchronous reset input for the TAP controller and debug support unit (DSU).

TRST* pin must be pulled down (ex. 10 k

Ω).

When this signal is deasserted, G-Bus timeout detection is disabled (refer to Section

“5.1.1 Detecting G-Bus Timeout”).

Input

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