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TMPR4938 bảng dữ liệu(PDF) 75 Page - Toshiba Semiconductor |
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TMPR4938 bảng dữ liệu(HTML) 75 Page - Toshiba Semiconductor |
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75 / 716 page ![]() Chapter 4 Address Mapping 4-3 4.2.3 Register Map Please refer to “10.5 PCI Configuration Space Register” about PCI configuration register. Table 4.2.2 Register Map Offset Address Peripheral Controller Detail 0x0000 to 0x4FFF Reserved ⎯ 0x5000 to 0x5FFF NDFMC Refer to “20.4” 0x6000 to 0x67FF SRAMC Refer to “21.4” 0x6800 to 0x6FFF Reserved ⎯ 0x7000 to 0x7FFF PCIC1 Refer to “16” (For ETHERC0 and ETHERC1) 0x8000 to 0x8FFF SDRAMC Refer to “9.4” 0x9000 to 0x9FFF EBUSC Refer to “7.4” 0xA000 to 0xAFFF ECC Refer to “9.4” 0xB000 to 0xB7FF DMAC0 Refer to “8.4” 0xB800 to 0xBFFF DMAC1 Refer to “8.4” 0xD000 to 0xDFFF PCIC Refer to “10.4” 0xE000 to 0xEFFF CONFIG Refer to “5.2” 0xF000 to 0xF0FF TMR0 Refer to “12.4” 0xF100 to 0xF1FF TMR1 Refer to “12.4” 0xF200 to 0xF2FF TMR2 Refer to “12.4” 0xF300 to 0xF3FF SIO0 Refer to “11.4” 0xF400 to 0xF4FF SIO1 Refer to “11.4” 0xF500 to 0xF50F PIO Refer to “13.4” 0xF510 to 0xF6FF IRC Refer to “15.4” 0xF700 to 0xF7FF ACLC Refer to “14.4” 0xF800 to 0xF8FF SPIC Refer to “17.4” 0xF900 to 0xFFFF Reserved |
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