TMPR4938 datasheet(91/716 Pages) TOSHIBA

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Chapter 5 Configuration Registers

5-3

5.2.1

Chip Configuration Register (CCFG)

0xE000

For the bit fields whose initial values are set by boot configuration (refer to Section 3.2), the initial

input signal level and the corresponding register value are indicated.

Reserved

: Type

: Initial value

Reserved

WDRST WDREXEN

BCFG

R/W1C R/W

: Type

DATA[15:8]

: Initial value

Reserved

GTOT

TINTDIS

PCI66 PCIMODE PCI1-66

DIVMODE

BEOW

R/W

R/W1C : Type

~DATA[7]

ADDR[19]

ADDR[3:0]

: Initial value

TOE PCIARB

PCIDIVMODE

Reserved PCI1DMD

SYSSP

Reserved

ENDIAN ARMODE ACEHOLD

R/W

R/W : Type

DATA[2]

ADDR[11:10]

ADDR[16]

ADDR[14:13]

ADDR[12]

: Initial value

Bit

Mnemonic

Field Name

Description

Initial Value Read/Write

63:42

⎯

Reserved

⎯

WDRST

Watchdog

Reset Status

Watch Dog Reset Status (Initial Value 0, RW1C)

Indicates that a watchdog reset has occurred (refer to Section

12.3.6).

Initialized when CGRESET* is asserted.

= No watchdog reset has occurred.

= A watchdog reset has occurred

R/W1C

WDREXEN

Watchdog

Reset External

Output

Watch Dog Reset External Enable (Initial Value 0, R/W)

Specifies whether to assert the WDRST* signal at a watchdog

reset (refer to Section 12.3.6).

Initialized when CGRESET* is asserted.

= Do not assert the WDRST* signal.

= Assert the WDRST* signal.

R/W

39:32

BCFG

Boot

Configuration

Set to 1 at a reset if the corresponding DATA[15:8] signal is

high.

Set to 0 at a reset if the corresponding DATA[15:8] signal is

low.

DATA[15:8]

31:27

⎯

Reserved

⎯

26:25

GTOT

G-Bus Timeout

Time

Specifies the number of G-Bus clock (GBUSCLK) cycles after

which a bus timeout error will occur on the internal bus (G-

Bus) of the TX4938.

= 4096 GBUSCLK

= 2048 GBUSCLK

= 1024 GBUSCLK

= 512 GBUSCLK

R/W

TINTDIS

Disable

TX49/H3 Core

Timer Interrupt

Indicates a value for indicating whether to enable the

TX49/H3 internal timer interrupt (refer to Section 15.3.5).

H: 0: The TX49/H3 internal timer interrupt is enabled.

L: 1: The TX49/H3 internal timer interrupt is disabled.

~DATA[7]

Figure 5.2.1 Chip Configuration Register (1/3)

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