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TMPR4938 bảng dữ liệu(PDF) 99 Page - Toshiba Semiconductor |
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TMPR4938 bảng dữ liệu(HTML) 99 Page - Toshiba Semiconductor |
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99 / 716 page  Chapter 5 Configuration Registers 5-11 5.2.5 Clock Control Register (CLKCTR) 0xE020 Bit 32 and bits 15-0 are reset bits for the on-chip peripheral modules. To bring on-chip peripheral modules out of the reset state, the corresponding bits must be cleared by software. Before clearing them, wait at least 128 CPU clock cycles after they are set. 63 50 49 48 Reserved 0 NDFCKD R/W R/W : Type : Initial value 47 34 33 32 Reserved 0 NDFRST R/W R/W : Type 0 0 : Initial value 31 26 25 24 23 22 21 20 19 18 17 16 ETH1CKD ETH0CKD SPICKD SRAMCKD PCI1CKD DMA1CKD ACLCKD PIOCKD DMACKD PCICCKD 1 TM0CKD TM1CKD TM2CKD SIO0CKD SIO1CKD R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W : Type 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 : Initial value 15 10 9 8 7 6 5 4 3 2 1 0 ETH1RST ETH0RST SPIRST SRAMRST PCI1RST DMA1RST ACLRST PIORST DMA0RST PCICRST 1 TM0RST TM1RST TM2RST SIO0RST SIO1RST R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W : Type 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 : Initial value Bit Mnemonic Field Name Description Initial Value Read/Write 63:50 ⎯ Reserved ⎯ ⎯ ⎯ 49 ⎯ ⎯ Always set this bit to 0. 0 R/W 48 NDFCKD NDFMC Clock Disable Controls clock pulses for the NAND Flash Memory controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. 0 R/W 47:34 ⎯ Reserved ⎯ ⎯ ⎯ 33 ⎯ ⎯ Always set this bit to 0. 0 R/W 32 NDFRST NDFMC Reset Resets the NAND Flash Memory controller. 0 = Normal state 1 = Reset 0 R/W 31 ETH1CKD ETHERC1 Clock Disable Controls clock pulses for the ETHERC1 controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. 0 R/W 30 ETH0CKD ETHERC0 Clock Disable Controls clock pulses for the ETHERC0 controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. 0 R/W 29 SPICKD SPIC Clock Disable Controls clock pulses for the SPI controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. 0 R/W 28 SRAMCKD SRAMC Clock Disable Controls clock pulses for the internal SRAM controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. 0 R/W 27 PCIC1CKD PCIC1 Clock Disable Controls clock pulses for PCI controller 1. 0 = Supply clock pulses. 1 = Do not supply clock pulses. 0 R/W 26 DMA1CKD DMAC1 Clock Disable Controls clock pulses for the DMA controller 1. 0 = Supply clock pulses. 1 = Do not supply clock pulses. 0 R/W Figure 5.2.5 Clock Control Register (1/3) |
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