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TMPR4938 bảng dữ liệu(PDF) 95 Page - Toshiba Semiconductor |
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TMPR4938 bảng dữ liệu(HTML) 95 Page - Toshiba Semiconductor |
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95 / 716 page  Chapter 5 Configuration Registers 5-7 5.2.3 Pin Configuration Register (PCFG) 0xE010 For the bit fields whose initial values are set by boot configuration (refer to Section 3.2), the initial input signal level and the corresponding register value are indicated. 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 ETH0_SEL ETH1_SEL ATA_SEL ISA_SEL SPI_SEL NDF_SEL Reserved DRVDATA DRVCB DRVDQM DRVADDR DRVCKE DRVRAS DRVCAS DRVWE DRVCS[3] R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W : Type ~DATA[3] ~DATA[6] 0 0 0 0 ADDR[4] ADDR[4] ADDR[4] ADDR[5] ADDR[5] ADDR[5] ADDR[5] ADDR[5] ADDR[5] : Initial value 47 45 44 41 40 39 33 32 DRVCS[2:0] DRVCK[3:0] DRVCKIN Reserved BYPASSPLL R/W R/W R/W R : Type ADDR[5] ADDR[5] ADDR[5] BYPASSPLL* : Initial value 31 30 29 28 27 26 23 22 21 16 Reserved SDCLKDLY SYSCLKEN SDCLKEN[3:0] SDCLKINEN PCICLKEN[5:0] R/W R/W R/W R/W R/W : Type 00 1 1111 0 111111 : Initial value 15 10 9 8 7 0 Reserved SEL2 SEL1 DMASEL3 DMASEL2 DMASEL1 DMASEL0 R R R/W R/W R/W R/W : Type ADDR[9] ADDR[18] 00 00 00 00 : Initial value Bit Mnemonic Field Name Description Initial Value Read/Write 63 ETH0_SEL Status of shared pin ETHERC0 Shared-pin status Indicates the status of shared pin. L : 1 : ETHERC0 selected H : 0 : ETHERC0 not selected ~DATA[3] R 62 ETH1_SEL Status of shared pin ETHERC1 Shared-pin status Indicates the status of shared pin. L : 1 : ETHERC1 selected H : 0 : ETHERC1 not selected ~DATA[6] R 61 ATA_SEL Setting of shared pin ATA/ISA Shared-pin setting Specifies the status of shared pin. 1 : ATA/ISA selected 0 : ATA/ISA not selected 0 R/W 60 ISA_SEL Setting of shared pin ISA Shared-pin setting Specifies the status of shared pin. 1 : ISA selected 0 : ISA not selected 0 R/W 59 SPI_SEL Setting of shared pin SPI Shared-pin setting Specifies the status of shared pin. 1 : SPI selected 0 : SPI not selected 0 R/W 58 NDF_SEL Setting of shared pin NDFMC Shared-pin setting Specifies the status of shared pin. When use NAND Flash IPL function, the initial value of this bit indicates 1 after booting. 1 : NDFMC selected 0 : NDFMC not selected 0 R/W 57 ⎯ Reserved ⎯ ⎯ ⎯ Figure 5.2.3 Pin Configuration Register (1/3) |
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