TMPR4938 datasheet(53/716 Pages) TOSHIBA

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Chapter 2 Configuration

2-1

Configuration

2.1

TX4938 block diagram

Figure 2.1.1 is an internal block diagram of the TX4938.

Figure 2.1.1 TX4938 Block Diagram

DMAC0

EBUSC

(8 channels)

EBIF

PLL

SDRAMC

(4 channels)

SIO

(2ch.)

IMB

WBU

DSU

TX49/H3 Core

I-Cache

D-Cache

G-Bus I/F

TMR2

PCIC

FPU

TIMER[1]

TIMER[0]

TCLK

NMI*

INT[5:0]

DMAREQ[3:0]

DMAACK[3:0]

DMADONE*

CTS[1:0]*

RTS[1:0]*

RXD[1:0]

TXD[1:0]

SCLK

PIO[15:0]

TEST

PIO

IRC

CE[7:0] *

ACE*

SWE*

OE*

BWE[3:0] *

BUSSPRT*

SDCLK[3:0]

RAS*

CAS*

SDCS[3:0]*

DQM[7:0]

WE*

CKE

SDCLKIN

DATA[63:0]

ADDR[19:0]

ACK*/READY

SYSCLK

IOR*, IOW* CS*[1;0]

CB[7:0]

RESET*

HALTDOZE

TDI

TCK

TDO

TMS

TRST*

DCLK

PCST[8:0]

TPC[3:1]

TEST[4:0]*

BYPASSPLL*

CGRESET*

MASTERCLK

ECC

PCIAD[31:0]

C_BE[3:0]

PAR

FRAME*

IRDY*

TRDY*

STOP*

ID_SEL

DEVSEL*

REQ[3:0]*

GNT[3:0]*

PERR*

SERR*

LOCK*

M66EN

PME*

EEPROM_DO

EEPROM_DI

EEPROM_CS

EEPROM_SK

PCICLK[5:0]

PCICLKIN

CPU core

PDMAC

TMR1

TMR0

ACLC

ACRESET*

SYNC

SDOUT

SDIN[1:0]

BITCLK

WDRST*

INTOUT

DMAC1

(4 channels)

ND_CLE, ND_ALE, ND_CE*,

ND_RE*, ND_WE*, ND_RB*

NDFMC

SRAM

(2kbx1)

E0TXD[3:0] (O) E0RXD[3:0] (I)

E0RXER (I), E0RXCLK (I) E0MDC (O)

E0RXDV (I) E0TXER (O) E0TXCLK (I)

E0MDIO (I/O) E0TXEN (O) E0CRS (I) E0COL(I)

PCIC1

ETHER

E1TXD[3:0] (O) E1RXD[3:0] (I)

E1RXER (I), E1RXCLK (I) E1MDC (O)

E1RXDV (I) E1TXER (O) E1TXCLK (I)

E1MDIO (I/O) E1TXEN (O) E1CRS (I) .E1COL(I)

SPIIN

SPIOUT

SPICLK

SPI

Internal PCI bus

Mask

ROM

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