TMPR4938 datasheet(51/716 Pages) TOSHIBA

51 / 716 page

Chapter 1 Overview and Features

1-5

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Can select either the Edge or Level interrupt detection mode for each external interrupt

•

Has a built-in 16-bit read/write register as a flag register for interrupt requests. Can request

interrupts to an external device or to the TX49/H3 core (IRC interrupt)

(10) Ethernet Controller

•

2-channel on-chip Ethernet interface

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Supports transfer rates of 100 Mbps or 10 Mbps

•

Supports MAC layers, employs the standard interface MII between physical layers and MAC

layers

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On-chip DMA

(11) NAND Flash Memory Controller

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Controls the NAND Flash Memory Interface by the register settings

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On-chip ECC (Error Correction Code) calculation circuit

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On-chip mask ROM, is bootable from NAND Flash Memory

(12) Serial Peripheral Interface (SPI)

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Full duplex, synchronous serial data transfer (I/O data, clock signals)

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Can specify 8-bit or 16-bit data length

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Programmable SPI baud rate

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Supports only Masters

(13) On-chip SRAM

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On-chip 2 KB SRAM

(14) Extended EJTAGInterface

The TX4938's Extended EJTAG (Extended Enhanced Joint Test Action Group) interface

provides two functions: IEEE1149.1-compliant JTAG boundary scan testing and real-time

debugging using the Debugging Support Unit (DSU) built into the TX49/H3 core.

•

IEEE 1149.1 JTAG Boundary Scan

•

Can use execution control (invoke, break, step, register/memory access) or PC tracing as real-

time debugging function that uses a dedicated emulation probe

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