TMPR4937 datasheet(301/552 Pages) TOSHIBA

301 / 552 page

Chapter 10 PCI Controller

10-43

10.4.18 PCI Status Interrupt Mask Register (PCIMASK) 0xD08C

Reserved

: Type

: Initial value

DPEIE SSEIE RMAIE RTAIE STAIE

Reserved

MDPEIE

Reserved

R/W

: Type

0x0

: Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

31:16

Reserved

⎯

DPEIE

Detected Parity

Error Interrupt

Enable

Detected Parity Error Interrupt Enable (Default: 0x0)

Generates an interrupt when a parity error is detected.

Usually, this interrupt is masked and a Master Data Parity error signals the

error to the system.

1: Generates an interrupt.

0: Does not generate an interrupt.

R/W

SSEIE

Signaled System

Error Interrupt

Enable

Signaled System Error Interrupt Enable (Default: 0x0)

Generates an interrupt when a system error is signaled.

1: Generates an interrupt.

0: Does not generate an interrupt.

R/W

RMAIE

Received Master

Abort Interrupt

Enable

Received Master Abort Interrupt Enable (Default: 0x0)

Generates an interrupt when a Master Abort is received.

1: Generates an interrupt.

0: Does not generate an interrupt.

R/W

RTAIE

Received Target

Abort Interrupt

Enable

Received Target Abort Interrupt Enable (Default: 0x0)

Generates an interrupt when a Target Abort is received.

1: Generates an interrupt.

0: Does not generate an interrupt.

R/W

STAIE

Signaled Target

Abort Interrupt

Enable

Signaled Target Abort Interrupt Enable (Default: 0x0)

Generates an interrupt when a Target Abort is signaled.

1: Generates an interrupt.

0: Does not generate an interrupt.

R/W

RMA

Received Master

Abort

Received Master Abort (Default: 0x0)

This is a shadow register of the PCISTATUS.RMA bit.

R/W

RTA

Received Target

Abort

Received Target Abort (Default: 0x0)

This is a shadow register of the PCISTATUS.RTA bit.

R/W

STA

Signaled Target

Abort

Signaled Target Abort (Default: 0x0)

This is a shadow register of the PCISTATUS.STA bit.

R/W

10:9

Reseved

⎯

MDPEIE

Master Data

Parity Detected

Interrupt Enable

Master Data Parity Detected Interrupt Enable (Default: 0x0)

Generates an interrupt when data parity is detected.

1: Generates an interrupt.

0: Does not generate an interrupt.

R/W

7:0

Reserved

⎯

Figure 10.4.16 PCI Status Interrupt Mask Register

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