TMPR4937 datasheet(300/552 Pages) TOSHIBA

300 / 552 page

Chapter 10 PCI Controller

10-42

10.4.17 Satellite Mode PCI Status Register (PCISSTATUS)

0xD088

The PCI Status, Command Register (PCISTATUS) or the PMCSR Register of the Configuration

Space cannot be accessed when the PCI Controller is in the Satellite mode. It is possible however to

read values from either of these registers.

Reserved

PMEEN

Reserved

: Type

0x0

: Initial value

DPE

SSE

RMA

RTA

STA

MDPE

Reserved

: Type

0x0

0x1

0x0

: Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

31:24

Reserved

⎯

25:24

Power State

PowerState (Default: 0x0)

This is a shadow register of the PowerState field in the PMCSR Register.

Note: Read this field in the following procedures. If other procedures are

used, incorrect data may be read.

(1) General procedures

After checking the P2GSTATUS.PMSC bit is set, read the PS field.

(2) Procedures to read at any time

To read PS field directly, but not using the procedures shown above (1),

read the PS field twice consecutively. Use the value if the same value is

read.

PMEEN

PME Enable

PME_En (Default: 0x0)

This is a shadow register of the PME_En bit of the PMCSR Register.

22:16

Reserved

⎯

DPE

Detected Parity

Error

Detected Parity Error (Default: 0x0)

This is a shadow register of the PCISTATUS.DPE bit.

SSE

Signaled System

Error

Signaled System Error (Default: 0x0)

This is a shadow register of the PCISTATUS.SSE bit.

RMA

Received Master

Abort

Received Master Abort (Default: 0x0)

This is a shadow register of the PCISTATUS.RMA bit.

RTA

Received Target

Abort

Received Target Abort (Default: 0x0)

This is a shadow register of the PCISTATUS.RTA bit.

STA

Signaled Target

Abort

Signaled Target Abort (Default: 0x0)

This is a shadow register of the PCISTATUS.STA bit.

10:9

Set DEVSEL

Timing

DEVSEL Timing (Fixed Value: 0x1)

This is a shadow register of the PCISTATUS.DT field.

MDPE

Data Parity

Detected

Master Data Parity Error Detected (Default: 0x0)

This is a shadow register of the PCISTATUS.MDPE bit.

7:0

Reserved

⎯

Figure 10.4.15 Satellite Mode PCI Status Register

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