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TMPR4937 bảng dữ liệu(PDF) 455 Page - Toshiba Semiconductor

tên linh kiện TMPR4937
Giải thích chi tiết về linh kiện  64-Bit TX System RISC TX49 Family
PDF  552 Pages
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nhà sản xuất  TOSHIBA [Toshiba Semiconductor]
Trang chủ  http://www.semicon.toshiba.co.jp/eng
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TMPR4937 bảng dữ liệu(HTML) 455 Page - Toshiba Semiconductor

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Chapter 15 Interrupt Controller
15-9
There are two flag registers: Flag Register 0 (IRFLAG0), and Flag Register 1 (IRFLAG1). These
registers have two different Write methods. Accordingly, Writes to one register are reflects in the other.
Either “0” or “1” can be written to Flag Register 0
In the case of Flag Register 1 however, “1” can be written from the TX49/H3 core, but “0” cannot be
written. On the other hand, bits that wrote “1” are cleared to “0” in the case of access from a device
other than the TX49/H3 core (access from an external PCI device for example). The bit value at this
time will not change even if “0” is written. This register sends interrupt notification from the TX49/H3
core to external devices. External devices can be used in applications that clear these interrupt
notifications.



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