TMPR4937 datasheet(451/552 Pages) TOSHIBA

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Chapter 15 Interrupt Controller

15-5

In addition to the above, the TX49/H3 core has a TX49/H3 core internal timer interrupt and two

software interrupts, but these interrupts are directly reported to the TX49/H3 core independently of this

Interrupt Controller. Please refer to the “64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core

Architecture” for more information.

15.3.2 Interrupt request detection

In order to perform interrupt detection, each register of the Interrupt Controller is initialized, then the

IDE bit of the Interrupt Detection Enable Register (IRDEN) is set to “1.” All interrupts detected by the

Interrupt Controller are masked when this bit is cleared.

It is possible to set each interrupt factor detection mode using Interrupt Detection Mode Register 0

(IRDM0) and Interrupt Detection Mode Register 1 (IRDM1). There are four detection modes: Low

level, High level, falling edge, and rising edge.

The detected interrupt factors can be read out from the Interrupt Pending Register (IRPND).

15.3.3 Interrupt level assigning

Interrupt levels from 0 to 7 are assigned to each detected interrupt using the Interrupt Level Register

(IRLVL0-7). Interrupt level 7 is the highest priority and interrupt level1 is the lowest priority. Level 0

interrupts will be masked. (Table 15.3.2).

The priorities set by these interrupt levels will be given higher priority than the priorities provided

for each interrupt source indicated in Table 15.3.1.

Table 15.3.2 Interrupt Levels

Priority

Interrupt Level

(IRLVLn.ILm)

High

111

110

101

100

011

010

Low

001

Mask

000

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