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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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PXAS30 bảng dữ liệu(PDF) 32 Page - NXP Semiconductors |
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PXAS30 bảng dữ liệu(HTML) 32 Page - NXP Semiconductors |
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32 / 52 page  Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range 2000 Dec 01 32 LSB MSB BIT SYMBOL FUNCTION RSTSRC.7 — Reserved for future use. Should not be set to 1 by user programs. RSTSRC.6 — Reserved for future use. Should not be set to 1 by user programs. RSTSRC.5 — Reserved for future use. Should not be set to 1 by user programs. RSTSRC.4 — Reserved for future use. Should not be set to 1 by user programs. RSTSRC.3 — Reserved for future use. Should not be set to 1 by user programs. RSTSRC.2 R_WD Indicates that the last reset was caused by a watchdog timer overflow. RSTSRC.1 R_CMD Indicates that the last reset was caused by execution of the RESET instruction. RSTSRC.0 R_EXT Indicates that the last reset was caused by the external RST input. — — — — RSTSRC Address:463h Not bit Addressable Reset Value: see below — R_WD R_CMD R_EXT SU00942 Figure 24. Reset source register (RSTSRC) INTERRUPTS XA-S3 interrupt sources include the following: • External interrupts 0 and 1 (2) • Timer 0, 1, and 2 interrupts (3) • PCA: 1 global and 5 channel interrupts (6) • A/D interrupt (1) • UART 0 transmitter and receiver interrupts (2) • UART 1 transmitter and receiver interrupts (2) • I2C interrupt (1) • Software interrupts (7) There are a total of 17 hardware interrupt sources, enable bits, priority bit sets, etc. The XA-S3 supports a total of 17 maskable event interrupt sources (for the various XA peripherals), seven software interrupts, 5 exception interrupts (plus reset), and 16 traps. The maskable event interrupts share a global interrupt disable bit (the EA bit in the IEL register) and each also has a separate individual interrupt enable bit (in the IEL or IEH registers). Only three bits of the IPA register values are used on the XA-S3. Each event interrupt can be set to occur at one of 8 priority levels via bits in the Interrupt Priority (IP) registers, IPA0 through IPA5. The value 0 in the IPA field gives the interrupt priority 0, in effect disabling the interrupt. A value of 1 gives the interrupt a priority of 9, the value 2 gives priority 10, etc. The result is the same as if all four bits were used and the top bit set for all values except 0. Details of the priority scheme may be found in the XA User Guide. The complete interrupt vector list for the XA-S3, including all 4 interrupt types, is shown in the following tables. The tables include the address of the vector for each interrupt, the related priority register bits (if any), and the arbitration ranking for that interrupt source. The arbitration ranking determines the order in which interrupts are processed if more than one interrupt of the same priority occurs simultaneously. EXCEPTION/TRAPS PRECEDENCE DESCRIPTION VECTOR ADDRESS ARBITRATION RANKING Reset (h/w, watchdog, s/w) 0000–0003 0 (High) Breakpoint 0004–0007 1 Trace 0008–000B 1 Stack Overflow 000C–000F 1 Divide by 0 0010–0013 1 User RETI 0014–0017 1 TRAP 0–15 (software) 0040–007F 1 |
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