PXAS30 datasheet(18/52 Pages) PHILIPS

18 / 52 page

Philips Semiconductors

Preliminary specification

XA-S3

XA 16-bit microcontroller

32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),

I2C, 2 UARTs, 16 MB address range

2000 Dec 01

I2C Interface

The I2C interface on the XA-S3 is identical to the standard byte-style

I2C interface found on devices such as the 8xC552 except for the

rate selection.

The I2C interface conforms to the 100 kHz I2C

specification, but may be used at rates up to 400 kHz

(non-conforming).

Important:

Before the I2C interface may be used, the port pins

P5.6 and 5.7, which correspond to the I2C functions SCL and SDA

respectively, must be set to the open drain mode.

The processor interfaces to the I2C logic via the following four

special function registers: I2CON (I2C control register), I2STA (I2C

status register), I2DAT (I2C data register), and I2ADR (I2C slave

address register). The I2C control logic interfaces to the external I2C

bus via two port 5 pins: P5.6/SCL (serial clock line) and P5.7/SDA

(serial data line).

The Control Register, I2CON

This register is shown in Figure 6. Two bits are affected by the I2C

hardware: the SI bit is set when a serial interrupt is requested, and

the STO bit is cleared when a STOP condition is present on the I2C

bus. The STO bit is also cleared when ENA = “0”.

ENA, the I2C Enable Bit

ENA = 0:

When ENA is “0”, the SDA and SCL outputs are not

driven. SDA and SCL input signals are ignored, SIO1 is in the “not

addressed” slave state, and the STO bit in I2CON is forced to “0”.

No other bits are affected. P5.6 and P5.7 may be used as open

drain I/O ports.

ENA = 1:

When ENA is “1”, SIO1 is enabled. The P5.6 and P5.7

port latches must be set to logic 1.

ENA should not be used to temporarily release the I2C-bus since,

when ENA is reset, the I2C-bus status is lost. The AA flag should be

used instead (see description of the AA flag in the following text).

In the following text, it is assumed the ENA = “1”.

STA, the START flag

STA = 1:

When the STA bit is set to enter a master mode, the I2C

hardware checks the status of the I2C bus and generates a START

condition if the bus is free. If the bus is not free, the I2C interface

waits for a STOP condition (which will free the bus) and generates a

START condition after a delay of a half clock period of the internal

serial clock generator.

If STA is set while the I2C interface is already in a master mode and

one or more bytes are transmitted or received, the hardware

transmits a repeated START condition. STA may be set at any time.

STA may also be set when the I2C interface is an addressed slave.

STA = 0:

When the STA bit is reset, no START condition or

repeated START condition will be generated.

STO, the STOP flag

STO = 1:

When the STO bit is set while the I2C interface is in a

master mode, a STOP condition is transmitted to the I2C bus. When

the STOP condition is detected on the bus, the hardware clears the

STO flag. In a slave mode, the STO flag may be set to recover from

an error condition. In this case, no STOP condition is transmitted to

the I2C bus. However, the hardware behaves as if a STOP condition

has been received and switches to the defined “not addressed” slave

receiver mode. The STO flag is automatically cleared by hardware.

If the STA and STO bits are both set, then a STOP condition is

transmitted to the I2C bus if the interface is in a master mode (in a

slave mode, the hardware generates an internal STOP condition

which is not transmitted). The I2C interface then transmits a START

condition.

STO = 0:

When the STO bit is reset, no STOP condition will be

generated.

SI, the Serial Interrupt flag

SI = 1:

When the SI flag is set, and the EA (interrupt system

enable) and EI2 (I2C interrupt enable) bits are also set, an I2C

interrupt is requested. SI is set by hardware when one of 25 of the

26 possible I2C interface states is entered. The only state that does

not cause SI to be set is state F8H, which indicates that no relevant

state information is available.

While SI is set, the low period of the serial clock on the SCL line is

stretched, and the serial transfer is suspended. A high level on the

SCL line is unaffected by the serial interrupt flag. SI must be reset

by software.

SI = 0:

When the SI flag is reset, no serial interrupt is requested,

and there is no stretching of the serial clock on the SCL line.

AA, the Assert Acknowledge flag

AA = 1:

If the AA flag is set, an acknowledge (low level to SDA) will

be returned during the acknowledge clock pulse on the SCL line when:

• The “own slave address” has been received.

• The general call address has been received while the general call

bit (GC) in I2ADR is set.

• A data byte has been received while the I2C interface is in the

master receiver mode.

• A data byte has been received while the I2C interface is in the

addressed slave receiver mode.

AA = 0:

If the AA flag is reset, a not acknowledge (high level to

SDA) will be returned during the acknowledge clock pulse on the

SCL line when:

• A data byte has been received while the I2C interface is in the

master receiver mode.

• A data byte has been received while the I2C interface is in the

addressed slave receiver mode.

When the I2C interface is in the addressed slave transmitter mode,

state C8H will be entered after the last serial data byte is

transmitted. When SI is cleared, the I2C interface leaves state C8H,

enters the not addressed slave receiver mode, and the SDA line

remains at a high level. In state C8H, the AA flag can be set again

for future address recognition.

When the I2C interface is in the not addressed slave mode, its own

slave address and the general call address are ignored. Consequently,

no acknowledge is returned, and a serial interrupt is not requested.

Thus, the hardware can be temporarily released from the I2C bus

while the bus status is monitored. While the hardware is released from

the bus, START and STOP conditions are detected, and serial data is

shifted in. Address recognition can be resumed at any time by setting

the AA flag. If the AA flag is set when the part’s own slave address or

the general call address has been partly received, the address will be

recognized at the end of the byte transmission.

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