PXAS30 datasheet(30/52 Pages) PHILIPS

30 / 52 page

Philips Semiconductors

Preliminary specification

XA-S3

XA 16-bit microcontroller

32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),

I2C, 2 UARTs, 16 MB address range

2000 Dec 01

1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be

selected at the same time by an address which has bit 0 = 0 (for

slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed

with 1100 0000.

In a more complex system the following could be used to select

slaves 1 and 2 while excluding slave 0:

Slave 0

SADDR

1100 0000

SADEN

1111 1001

Given

1100 0XX0

Slave 1

SADDR

1110 0000

SADEN

1111 1010

Given

1110 0X0X

Slave 2

SADDR

1110 0000

SADEN

1111 1100

Given

1110 00XX

In the above example the differentiation among the 3 slaves is in the

lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be

uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and

it can be uniquely addressed by 1110 and 0101. Slave 2 requires

that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0

and 1 and exclude Slave 2 use address 1110 0100, since it is

necessary to make bit 2 = 1 to exclude slave 2.

The Broadcast Address for each slave is created by taking the

logical OR of SADDR and SADEN. Zeros in this result are teated as

don’t-cares. In most cases, interpreting the don’t-cares as ones, the

broadcast address will be FF hexadecimal.

Upon reset SADDR and SADEN are loaded with 0s. This produces

a given address of all “don’t cares” as well as a Broadcast address

of all “don’t cares”. This effectively disables the Automatic

Addressing mode and allows the microcontroller to use standard

UART drivers which do not make use of this feature.

BIT

SYMBOL

FUNCTION

SnCON.5

SM2

Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1, then RI

will not be activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2=1 then RI will not be activated if a

valid stop bit was not received. In Mode 0, SM2 should be 0.

SnCON.4

REN

Enables serial reception. Set by software to enable reception. Clear by software to disable reception.

SnCON.3

TB8

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. The TB8 bit is not

double buffered. See text for details.

SnCON.2

RB8

In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, if SM2=0, RB8 is the stop bit that was

received. In Mode 0, RB8 is not used.

SnCON.1

Transmit interrupt flag. Set when another byte may be written to the UART transmitter. See text for details.

Must be cleared by software.

SnCON.0

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the end of the stop bit time

in the other modes (except see SM2). Must be cleared by software.

Where SM0, SM1 specify the serial port mode, as follows:

SM0

SM1

Mode

Description

Baud Rate

shift register

fOSC/16

8-bit UART

variable

9-bit UART

fOSC/32

9-bit UART

variable

SU00597C

RB8

TB8

REN

SM2

SM1

SM0

SnCON

Address:

S0CON 420

S1CON 424

Bit Addressable

Reset Value: 00H

LSB

MSB

Figure 21. Serial Port Control (SnCON) Register

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