PXAS30 datasheet(28/52 Pages) PHILIPS

28 / 52 page

Philips Semiconductors

Preliminary specification

XA-S3

XA 16-bit microcontroller

32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),

I2C, 2 UARTs, 16 MB address range

2000 Dec 01

Serial Port Control Register

The serial port control and status register is the Special Function

the mode selection bits, but also the 9th data bit for transmit and

receive (TB8_n and RB8_n), and the serial port interrupt bits (TI_n

and RI_n).

TI Flag

In order to allow easy use of the double buffered UART transmitter

feature, the TI_n flag is set by the UART hardware under two

conditions. The first condition is the completion of any byte

transmission. This occurs at the end of the stop bit in modes 1, 2, or

3, or at the end of the eighth data bit in mode 0. The second

condition is when SnBUF is written while the UART transmitter is

idle. In this case, the TI_n flag is set in order to indicate that the

second UART transmitter buffer is still available.

Typically, UART transmitters generate one interrupt per byte

transmitted. In the case of the XA UART, one additional interrupt is

generated as defined by the stated conditions for setting the TI_n

flag. This additional interrupt does not occur if double buffering is

bypassed as explained below. Note that if a character oriented

approach is used to transmit data through the UART, there could be

a second interrupt for each character transmitted, depending on the

timing of the writes to SBUF. For this reason, it is generally better to

bypass double buffering when the UART transmitter is used in

character oriented mode. This is also true if the UART is polled

rather than interrupt driven, and when transmission is character

oriented rather than message or string oriented. The interrupt occurs

at the end of the last byte transmitted when the UART becomes idle.

Among other things, this allows a program to determine when a

message has been transmitted completely. The interrupt service

routine should handle this additional interrupt.

The recommended method of using the double buffering in the

application program is to have the interrupt service routine handle a

single byte for each interrupt occurrence. In this manner the program

essentially does not require any special considerations for double

buffering. Unless higher priority interrupts cause delays in the servicing

of the UART transmitter interrupt, the double buffering will result in

transmitted bytes being tightly packed with no intervening gaps.

9-bit Mode

Please note that the ninth data bit (TB8) is not double buffered. Care

must be taken to insure that the TB8 bit contains the intended data

at the point where it is transmitted. Double buffering of the UART

transmitter may be bypassed as a simple means of synchronizing

TB8 to the rest of the data stream.

Bypassing Double Buffering

The UART transmitter may be used as if it is single buffered. The

recommended UART transmitter interrupt service routine (ISR)

technique to bypass double buffering first clears the TI_n flag upon

entry into the ISR, as in standard practice. This clears the interrupt

that activated the ISR. Secondly, the TI_n flag is cleared immediately

following each write to SnBUF. This clears the interrupt flag that would

otherwise direct the program to write to the second transmitter buffer.

If there is any possibility that a higher priority interrupt might become

active between the write to SnBUF and the clearing of the TI_n flag,

the interrupt system may have to be temporarily disabled during that

sequence by clearing, then setting the EA bit in the IEL register.

CLOCKING SCHEME/BAUD RATE GENERATION

The XA UARTS clock rates are determined by either a fixed division

(modes 0 and 2) of the oscillator clock or by the Timer 1 or Timer 2

overflow rate (modes 1 and 3).

The clock for the UARTs in XA runs at 16x the Baud rate. If the

timers are used as the source for Baud Clock, since maximum

speed of timers/Baud Clock is Osc/4, the maximum baud rate is

timer overflow divided by 16 i.e. Osc/64.

In Mode 0, it is fixed at Osc/16. In Mode 2, however, the fixed rate

is Osc/32.

Osc/4

Pre-scaler

for all Timers T0 1 2

Osc/16

for all Timers T0,1,2

controlled by PT1, PT0

Osc/64

controlled by PT1, PT0

bits in SCR

reserved

Baud Rate for UART Mode 0:

Baud_Rate = Osc/16

Baud Rate calculation for UART Mode 1 and 3:

Baud_Rate = Timer_Rate/16

Timer_Rate = Osc/(N*(Timer_Range– Timer_Reload_Value))

where N = the TCLK prescaler value: 4, 16, or 64.

and Timer_Range =

256 for timer 1 in mode 2.

65536 for timer 1 in mode 0 and timer 2

in count up mode.

The timer reload value may be calculated as follows:

Timer_Reload_Value = Timer_Range–(Osc/(Baud_Rate*N*16))

NOTES:

1.. The maximum baud rate for a UART in mode 1 or 3 is Osc/64.

2.. The lowest possible baud rate (for a given oscillator frequency

and N value) may be found by using a timer reload value of 0.

3.. The timer reload value may never be larger than the timer range.

4.. If a timer reload value calculation gives a negative or fractional

result, the baud rate requested is not possible at the given

oscillator frequency and N value.

Baud Rate for UART Mode 2:

Baud_Rate = Osc/32

Using Timer 2 to Generate Baud Rates

Timer T2 is a 16-bit up/down counter in XA. As a baud rate

generator, timer 2 is selected as a clock source for either/both

UART0 and UART1 transmitters and/or receivers by setting TCLKn

and/or RCLKn in T2CON and T2MOD. As the baud rate generator,

T2 is incremented as Osc/N where N = 4, 16 or 64 depending on

TCLK as programmed in the SCR bits PT1, and PTO. So, if T2 is

the source of one UART, the other UART could be clocked by either

T1 overflow or fixed clock, and the UARTs could run independently

with different baud rates.

T2CON

bit5

bit4

0x418

RCLK0

TCLK0

T2MOD

bit5

bit4

0x419

RCLK1

TCLK1

Prescaler Select for Timer Clock (TCLK)

SCR

bit3

bit2

0x440

PT1

PT0

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