PIC18F44J10-ESLASHML datasheet(155/358 Pages) MICROCHIP

155 / 358 page

Preliminary

DS39682C-page 153

PIC18F45J10 FAMILY

15.3.8

OPERATION IN POWER-MANAGED

MODES

In SPI Master mode, module clocks may be operating

at a different speed than when in full power mode; in

the case of Sleep mode, all clocks are halted.

In Idle modes, a clock is provided to the peripherals.

That clock should be from the primary clock source, the

secondary clock (Timer1 oscillator at 32.768 kHz) or

the INTOSC source. See Section 2.6 “Clock Sources

and Oscillator Switching” for additional information.

In most cases, the speed that the master clocks SPI

data is not important; however, this should be

evaluated for each system.

If MSSP interrupts are enabled, they can wake the con-

troller from Sleep mode, or one of the Idle modes, when

the master completes sending data. If an exit from

Sleep or Idle mode is not desired, MSSP interrupts

should be disabled.

If the Sleep mode is selected, all module clocks are

halted and the transmission/reception will remain in

that state until the devices wakes. After the device

returns to Run mode, the module will resume

transmitting and receiving data.

In SPI Slave mode, the SPI Transmit/Receive Shift

allows the device to be placed in any power-managed

mode

and

data

shifted

into

the

SPI

Transmit/Receive Shift register. When all 8 bits have

been received, the MSSP interrupt flag bit will be set

and if enabled, will wake the device.

15.3.9

EFFECTS OF A RESET

A Reset disables the MSSP module and terminates the

current transfer.

15.3.10

BUS MODE COMPATIBILITY

Table 15-1 shows the compatibility between the

standard SPI modes and the states of the CKP and

CKE control bits.

TABLE 15-1:

SPI™ BUS MODES

There is also an SMP bit which controls when the data

is sampled.

15.3.11

SPI CLOCK SPEED AND MODULE

INTERACTIONS

Because

MSSP1

and

MSSP2

are

independent

modules, they can operate simultaneously at different

data rates. Setting the SSPM3:SSPM0 bits of the

SSPxCON1 register determines the rate for the

corresponding module.

An exception is when both modules use Timer2 as a

time base in Master mode. In this instance, any

changes to the Timer2 operation will affect both MSSP

modules equally. If different bit rates are required for

each module, the user should select one of the other

three time base options for one of the modules.

Standard SPI™ Mode

Terminology

Control Bits State

CKP

CKE

0, 0

0, 1

1, 0

1, 1

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