PIC18F44J10-ESLASHML datasheet(131/358 Pages) MICROCHIP

131 / 358 page

Preliminary

DS39682C-page 129

PIC18F45J10 FAMILY

The CCPRxH register and a 2-bit internal latch are

used to double-buffer the PWM duty cycle. This

double-buffering is essential for glitchless PWM

operation.

When the CCPRxH and 2-bit latch match TMR2,

concatenated with an internal 2-bit Q clock or 2 bits of

the TMR2 prescaler, the CCPx pin is cleared.

The maximum PWM resolution (bits) for a given PWM

frequency is given by the equation:

EQUATION 13-3:

TABLE 13-4:

EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

13.4.3

PWM AUTO-SHUTDOWN

(CCP1 ONLY)

The PWM auto-shutdown features of the Enhanced CCP

module are also available to CCP1 in 28-pin devices. The

operation of this feature is discussed in detail in

Section 14.4.7 “Enhanced PWM Auto-Shutdown”.

Auto-shutdown features are not available for CCP2.

13.4.4

SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for PWM operation:

Set the PWM period by writing to the PR2

Set the PWM duty cycle by writing to the

CCPRxL register and CCPxCON<5:4> bits.

Make the CCPx pin an output by clearing the

appropriate TRIS bit.

Set the TMR2 prescale value, then enable

Timer2 by writing to T2CON.

Configure the CCPx module for PWM operation.

Note:

If the PWM duty cycle value is longer than

the PWM period, the CCP2 pin will not be

cleared.

FOSC

FPWM

---------------

⎝⎠

⎛⎞

log

()

log

-----------------------------bits

PWM Resolution (max)

PWM Frequency

2.44 kHz

9.77 kHz

39.06 kHz

156.25 kHz

312.50 kHz

416.67 kHz

Timer Prescaler (1, 4, 16)

41111

PR2 Value

FFh

3Fh

1Fh

17h

Maximum Resolution (bits)

6.58

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