PIC18F44J10-ESLASHML datasheet(128/358 Pages) MICROCHIP

128 / 358 page

PIC18F45J10 FAMILY

DS39682C-page 126

Preliminary

13.3

Compare Mode

In Compare mode, the 16-bit CCPRx register value is

constantly compared against the TMR1 register value.

When a match occurs, the CCPx pin can be:

• driven high

• driven low

• toggled (high-to-low or low-to-high)

• remain unchanged (that is, reflects the state of the

I/O latch)

The action on the pin is based on the value of the mode

select bits (CCPxM3:CCPxM0). At the same time, the

interrupt flag bit, CCPxIF, is set.

13.3.1

CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the appropriate TRIS bit.

13.3.2

TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

13.3.3

SOFTWARE INTERRUPT MODE

When the Generate Software Interrupt mode is chosen

(CCPxM3:CCPxM0 = 1010), the corresponding CCPx

pin is not affected. Only a CCP interrupt is generated,

if enabled and the CCPxIE bit is set.

13.3.4

SPECIAL EVENT TRIGGER

Both CCP modules are equipped with a Special Event

Trigger. This is an internal hardware signal generated

in Compare mode to trigger actions by other modules.

The Special Event Trigger is enabled by selecting

the

Compare

Special

Event

Trigger

mode

(CCPxM3:CCPxM0 = 1011).

For either CCP module, the Special Event Trigger resets

the Timer register pair for whichever timer resource is

currently assigned as the module’s time base. This

allows the CCPRx registers to serve as a programmable

period register for either timer.

The Special Event Trigger for CCP2 can also start an

A/D conversion. In order to do this, the A/D converter

must already be enabled.

FIGURE 13-2:

COMPARE MODE OPERATION BLOCK DIAGRAM

Note:

Clearing the CCP2CON register will force

the RB3 or RC1 compare output latch

(depending on device configuration) to the

default low level. This is not the PORTB or

PORTC I/O data latch.

CCPR1H

CCPR1L

TMR1H

TMR1L

Comparator

Output

Logic

Special Event Trigger

Set CCP1IF

CCP1 pin

TRIS

CCP1CON<3:0>

Output Enable

CCPR2H

CCPR2L

Comparator

Set CCP2IF

Compare

(Timer1 Reset)

Output

Logic

Special Event Trigger

CCP2 pin

TRIS

CCP2CON<3:0>

Output Enable

(Timer1 Reset, A/D Trigger)

Match

Compare

Match

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