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PIC18F44J10-E/ML bảng dữ liệu(PDF) 318 Page - Microchip Technology

tên linh kiện PIC18F44J10-E/ML
Giải thích chi tiết về linh kiện  28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
PDF  358 Pages
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nhà sản xuất  MICROCHIP [Microchip Technology]
Trang chủ  http://www.microchip.com
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PIC18F44J10-E/ML bảng dữ liệu(HTML) 318 Page - Microchip Technology

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PIC18F45J10 FAMILY
DS39682C-page 316
Preliminary
© 2007 Microchip Technology Inc.
FIGURE 23-9:
CAPTURE/COMPARE/PWM TIMINGS (INCLUDING ECCP MODULE)
TABLE 23-12: CAPTURE/COMPARE/PWM REQUIREMENTS (INCLUDING ECCP MODULE)
TABLE 23-13: PARALLEL SLAVE PORT REQUIREMENTS
Note:
Refer to Figure 23-3 for load conditions.
CCPx
(Capture Mode)
50
51
52
CCPx
53
54
(Compare or PWM Mode)
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
50
TCCL
CCPx Input Low
Time
No prescaler
0.5 TCY + 20
—
ns
With prescaler
10
—
ns
51
TCCH
CCPx Input
High Time
No prescaler
0.5 TCY + 20
—
ns
With prescaler
10
—
ns
52
TCCP
CCPx Input Period
3 TCY + 40
N
—
ns
N = prescale
value (1, 4 or 16)
53
TCCR
CCPx Output Fall Time
—
25
ns
54
TCCF
CCPx Output Fall Time
—
25
ns
Param.
No.
Symbol
Characteristic
Min
Max
Units
Conditions
62
TdtV2wrH
Data In Valid before WR
↑ or CS ↑ (setup time)
20
—
ns
63
TwrH2dtI
WR
↑ or CS ↑ to Data–In Invalid (hold time)
20
—
ns
64
TrdL2dtV
RD
↓ and CS ↓ to Data–Out Valid
—
80
ns
65
TrdH2dtI
RD
↑ or CS ↓ to Data–Out Invalid
10
30
ns
66
TibfINH
Inhibit of the IBF Flag bit being Cleared from
WR
↑ or CS ↑
—3 TCY



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