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PIC18F44J10-E/ML bảng dữ liệu(PDF) 315 Page - Microchip Technology

tên linh kiện PIC18F44J10-E/ML
Giải thích chi tiết về linh kiện  28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
PDF  358 Pages
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nhà sản xuất  MICROCHIP [Microchip Technology]
Trang chủ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F44J10-E/ML bảng dữ liệu(HTML) 315 Page - Microchip Technology

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© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 313
PIC18F45J10 FAMILY
FIGURE 23-5:
CLKO AND I/O TIMING
TABLE 23-9:
CLKO AND I/O TIMING REQUIREMENTS
Note:
Refer to Figure 23-3 for load conditions.
OSC1
CLKO
I/O pin
(Input)
I/O pin
(Output)
Q4
Q1
Q2
Q3
10
13
14
17
20, 21
19
18
15
11
12
16
Old Value
New Value
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units Conditions
10
TOSH2CKLOSC1
↑ to CLKO ↓
—
75
200
ns
11
TOSH2CKHOSC1
↑ to CLKO ↑
—
75
200
ns
12
TCKR
CLKO Rise Time
—
15
30
ns
13
TCKF
CLKO Fall Time
—
15
30
ns
14
TCKL2IOVCLKO
↓ to Port Out Valid
—
—
0.5 TCY + 20
ns
15
TIOV2CKH Port In Valid before CLKO
↑
0.25 TCY + 25
—
—
ns
16
TCKH2IOI
Port In Hold after CLKO
↑
0—
—
ns
17
TOSH2IOVOSC1
↑ (Q1 cycle) to Port Out Valid
—
50
150
ns
18
TOSH2IOIOSC1
↑ (Q2 cycle) to Port Input Invalid
(I/O in hold time)
100
—
—
ns
18A
200
—
—
ns
19
TIOV2OSH Port Input Valid to OSC1
↑
(I/O in setup time)
0—
—
ns
20
TIOR
Port Output Rise Time
—
TBD
6
ns
21
TIOF
Port Output Fall Time
—
TBD
5
ns
22†
TINP
INT pin High or Low Time
TCY
——
ns
23†
TRBP
RB7:RB4 Change INT High or Low Time
TCY
——
ns
Legend: TBD = To Be Determined
† These parameters are asynchronous events not related to any internal clock edges.



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