PIC18F44J10-ESLASHML datasheet(285/358 Pages) MICROCHIP

285 / 358 page

Preliminary

DS39682C-page 283

PIC18F45J10 FAMILY

21.2

Extended Instruction Set

In addition to the standard 75 instructions of the PIC18

instruction set, PIC18F45J10 family devices also

provide an optional extension to the core CPU function-

ality. The added features include eight additional

instructions

that

augment

indirect

and

indexed

addressing operations and the implementation of

Indexed Literal Offset Addressing mode for many of the

standard PIC18 instructions.

The additional features of the extended instruction set

are disabled by default. To enable them, users must set

the XINST configuration bit.

The instructions in the extended set can all be

classified as literal operations, which either manipulate

the File Select Registers, or use them for indexed

addressing. Two of the instructions, ADDFSR and

SUBFSR

, each have an additional special instantiation

for using FSR2. These versions (ADDULNK and

SUBULNK

) allow for automatic return after execution.

The extended instructions are specifically implemented

to optimize re-entrant program code (that is, code that

is recursive or that uses a software stack) written in

high-level languages, particularly C. Among other

things,

they

allow

users

working

high-level

languages to perform certain operations on data

structures more efficiently. These include:

• dynamic allocation and deallocation of software

stack space when entering and leaving

subroutines

• function pointer invocation

• software stack pointer manipulation

• manipulation of variables located in a software

stack

A summary of the instructions in the extended instruc-

tion set is provided in Table 21-3. Detailed descriptions

are provided in Section 21.2.2 “Extended Instruction

Set”. The opcode field descriptions in Table 21-1

(page 242) apply to both the standard and extended

PIC18 instruction sets.

21.2.1

EXTENDED INSTRUCTION SYNTAX

Most of the extended instructions use indexed argu-

ments, using one of the File Select Registers and some

offset to specify a source or destination register. When

an argument for an instruction serves as part of

indexed addressing, it is enclosed in square brackets

(“[ ]”). This is done to indicate that the argument is used

as an index or offset. MPASM™ Assembler will flag an

error if it determines that an index or offset value is not

bracketed.

When the extended instruction set is enabled, brackets

are also used to indicate index arguments in byte-

oriented and bit-oriented instructions. This is in addition

to other changes in their syntax. For more details, see

Section 21.2.3.1 “Extended Instruction Syntax with

Standard PIC18 Commands”.

TABLE 21-3:

EXTENSIONS TO THE PIC18 INSTRUCTION SET

Note:

The instruction set extension and the

Indexed Literal Offset Addressing mode

were designed for optimizing applications

written in C; the user may likely never use

these instructions directly in assembler.

The syntax for these commands is pro-

vided as a reference for users who may be

reviewing code that has been generated

by a compiler.

Note:

In the past, square brackets have been

used to denote optional arguments in the

PIC18 and earlier instruction sets. In this

text

and

going

forward,

optional

arguments are denoted by braces (“{ }”).

Mnemonic,

Operands

Description

Cycles

16-Bit Instruction Word

Status

Affected

MSb

LSb

ADDFSR

ADDULNK

CALLW

MOVSF

MOVSS

PUSHL

SUBFSR

SUBULNK

f, k

zs, fd

zs, zd

f, k

Add literal to FSR

Add literal to FSR2 and return

Call subroutine using WREG

Move zs (source) to 1st word

fd (destination)

2nd word

Move zs (source) to 1st word

zd (destination)

2nd word

Store literal at FSR2,

decrement FSR2

Subtract literal from FSR

Subtract literal from FSR2 and

return

1110

0000

1110

1111

1110

1111

1110

1000

0000

1011

ffff

1011

xxxx

1010

1001

ffkk

11kk

0001

0zzz

ffff

1zzz

xzzz

kkkk

ffkk

11kk

kkkk

0100

zzzz

ffff

zzzz

kkkk

None

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