PIC18F44J10-ESLASHML datasheet(283/358 Pages) MICROCHIP

283 / 358 page

Preliminary

DS39682C-page 281

PIC18F45J10 FAMILY

TSTFSZ

Test f, Skip if 0

Syntax:

TSTFSZ f {,a}

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

skip if f = 0

Status Affected:

None

Encoding:

0110

011a

ffff

Description:

If ‘f’ = 0, the next instruction fetched

during the current instruction execution

is discarded and a NOP is executed,

making this a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

≤ 95 (5Fh). See

Section 21.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Decode

Read

Process

Data

operation

If skip:

operation

If skip and followed by 2-word instruction:

operation

Example:

HERE

TSTFSZ

CNT, 1

NZERO

ZERO

Before Instruction

Address (HERE)

After Instruction

If CNT

00h,

Address (ZERO)

If CNT

≠

00h,

Address (NZERO)

XORLW

Exclusive OR Literal with W

Syntax:

XORLW k

Operands:

≤ k ≤ 255

Operation:

(W) .XOR. k

→ W

Status Affected:

N, Z

Encoding:

0000

1010

kkkk

Description:

The contents of W are XORed with

the 8-bit literal ‘k’. The result is placed

in W.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

literal ‘k’

Process

Data

Write to W

Example:

XORLW

0AFh

Before Instruction

B5h

After Instruction

1Ah

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