PIC18F44J10-ESLASHML datasheet(259/358 Pages) MICROCHIP

259 / 358 page

Preliminary

DS39682C-page 257

PIC18F45J10 FAMILY

CLRF

Clear f

Syntax:

CLRF

f {,a}

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

000h

→ f

→ Z

Status Affected:

Encoding:

0110

101a

ffff

Description:

Clears the contents of the specified

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

≤ 95 (5Fh). See

Section 21.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write

Example:

CLRF

FLAG_REG, 1

Before Instruction

FLAG_REG

5Ah

After Instruction

FLAG_REG

00h

CLRWDT

Clear Watchdog Timer

Syntax:

CLRWDT

Operands:

None

Operation:

000h

→ WDT,

000h

→ WDT postscaler,

→ TO,

→ PD

Status Affected:

TO, PD

Encoding:

0000

0100

Description:

CLRWDT

instruction resets the

Watchdog Timer. It also resets the

postscaler of the WDT. Status bits, TO

and PD, are set.

Words:

Cycles:

Q Cycle Activity:

Decode

operation

Process

Data

operation

Example:

CLRWDT

Before Instruction

WDT Counter

After Instruction

WDT Counter

00h

WDT Postscaler

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