MC68HC908GR4MP datasheet(170/286 Pages) FREESCALE

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Serial Communications Interface (SCI)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

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Freescale Semiconductor

If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.

To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and

RT10. Table 18-3 summarizes the results of the data bit samples.

NOTE

The RT8, RT9, and RT10 samples do not affect start bit verification. If any

or all of the RT8, RT9, and RT10 start bit samples are 1s following a

successful start bit verification, the noise flag (NF) is set and the receiver

assumes that the bit is a start bit.

To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 18-4

summarizes the results of the stop bit samples.

18.4.3.4 Framing Errors

If the data recovery logic does not detect a 1 where the stop bit should be in an incoming character, it sets

the framing error bit, FE, in SCS1. A break character also sets the FE bit because a break character has

no stop bit. The FE bit is set at the same time that the SCRF bit is set.

101

110

111

Table 18-3. Data Bit Recovery

RT8, RT9, and RT10 Samples

Data Bit Determination

Noise Flag

000

001

010

011

100

101

110

111

Table 18-4. Stop Bit Recovery

RT8, RT9, and RT10

Samples

Framing

Error Flag

Noise Flag

000

001

010

011

100

101

110

111

Table 18-2. Start Bit Verification (Continued)

RT3, RT5, and RT7 Samples

Start Bit

Verification

Noise Flag

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