MC68HC908GR4MP datasheet(136/286 Pages) FREESCALE

136 / 286 page

Monitor ROM (MON)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

136

Freescale Semiconductor

15.3.2 Data Format

Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.

Transmit and receive baud rates must be identical.

Figure 15-3. Monitor Data Format

15.3.3 Break Signal

A start bit (0) followed by nine 0 bits is a break signal. When the monitor receives a break signal, it drives

the PTA0 pin high for the duration of two bits and then echoes back the break signal.

Figure 15-4. Break Transaction

15.3.4 Baud Rate

The communication baud rate is controlled by the crystal frequency upon entry into monitor mode. The

divide by ratio is 1024.

If monitor mode was entered with VDD on IRQ, then the divide by ratio is also set at 1024. If monitor mode

was entered with VSS on IRQ, then the internal PLL steps up the external frequency, presumed to be

32.768 kHz, to 2.4576 MHz. These latter two conditions for monitor mode entry require that the reset

vector is blank.

Table 15-3 lists external frequencies required to achieve a standard baud rate of 9600 BPS. Other

standard baud rates can be accomplished using proportionally higher or lower frequency generators. If

using a crystal as the clock source, be aware of the upper frequency limit that the internal clock module

can handle. See 23.6 5.0 V Control Timing and 23.7 3.0 V Control Timing for this limit.

Table 15-3. Monitor Baud Rate Selection

External

Frequency

IRQ

Internal

Frequency

Baud Rate

(BPS)

9.8304 MHz

VTST

2.4576 MHz

9600

9.8304 MHz

VDD

2.4576 MHz

9600

32.768 kHz

VSS

2.4576 MHz

9600

BIT 5

START

BIT

BIT 1

STOP

BIT

START

BIT

BIT 2

BIT 3

BIT 4

BIT 7

BIT 0

BIT 6

MISSING STOP BIT

2-STOP BIT DELAY BEFORE ZERO ECHO

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