MC68HC908GR4MP datasheet(225/286 Pages) FREESCALE

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MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

225

Chapter 21

Timebase Module (TBM)

21.1 Introduction

This section describes the timebase module (TBM). The TBM will generate periodic interrupts at user

selectable rates using a counter clocked by the external crystal clock. This TBM version uses 15 divider

stages, eight of which are user selectable.

For further information regarding timers on M68HC08 family devices, please consult the HC08 Timer

Reference Manual, TIM08RM/AD.

21.2 Features

Features of the TBM module include:

•

Software programmable 1 Hz, 4 Hz, 16 Hz, 256 Hz, 512 Hz, 1024 Hz, 2048 Hz, and 4096 Hz

periodic interrupt using external 32.768 kHz crystal

•

User selectable oscillator clock source enable during stop mode to allow periodic wakeup from stop

21.3 Functional Description

NOTE

This module is designed for a 32.768 kHz oscillator.

This module can generate a periodic interrupt by dividing the crystal frequency, CGMXCLK. The counter

is initialized to all 0s when TBON bit is cleared. The counter, shown in Figure 21-1, starts counting when

the TBON bit is set. When the counter overflows at the tap selected by TBR2:TBR0, the TBIF bit gets set.

If the TBIE bit is set, an interrupt request is sent to the CPU. The TBIF flag is cleared by writing a 1 to the

TACK bit. The first time the TBIF flag is set after enabling the timebase module, the interrupt is generated

at approximately half of the overflow period. Subsequent events occur at the exact period.

The timebase module may remain active after execution of the STOP instruction if the crystal oscillator

has been enabled to operate during stop mode through the OSCSTOPENB bit in the configuration

21.4 Interrupts

The timebase module can periodically interrupt the CPU with a rate defined by TBR2:TBR0. When the

timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase

interrupt, the counter chain overflow will generate a CPU interrupt request.

NOTE

Interrupts must be acknowledged by writing a 1 to the TACK bit.

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