MC68HC908GR4MP datasheet(218/286 Pages) FREESCALE

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Serial Peripheral Interface (SPI)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

218

Freescale Semiconductor

The following sources in the SPI status and control register can generate CPU interrupt requests:

•

SPI receiver full bit (SPRF) — The SPRF bit becomes set every time a byte transfers from the shift

SPRF generates an SPI receiver/error CPU interrupt request.

•

SPI transmitter empty (SPTE) — The SPTE bit becomes set every time a byte transfers from the

transmit data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set,

SPTE generates an SPTE CPU interrupt request.

20.9 Resetting the SPI

Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is 0.

Whenever SPE is low, the following occurs:

•

The SPTE flag is set.

•

Any transmission currently in progress is aborted.

•

The shift register is cleared.

•

The SPI state counter is cleared, making it ready for a new complete transmission.

•

All the SPI port logic is defaulted back to being general-purpose I/O.

These items are reset only by a system reset:

•

All control bits in the SPCR register

•

All control bits in the SPSCR register (MODFEN, ERRIE, SPR1, and SPR0)

•

The status flags SPRF, OVRF, and MODF

By not resetting the control bits when SPE is low, the user can clear SPE between transmissions without

having to set all control bits again when SPE is set back high for the next transmission.

By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the

SPI has been disabled. The user can disable the SPI by writing 0 to the SPE bit. The SPI can also be

disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set.

20.10 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-consumption standby modes.

20.10.1 Wait Mode

The SPI module remains active after the execution of a WAIT instruction. In wait mode the SPI module

registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can

bring the MCU out of wait mode.

If SPI module functions are not required during wait mode, reduce power consumption by disabling the

SPI module before executing the WAIT instruction.

To exit wait mode when an overflow condition occurs, enable the OVRF bit to generate CPU interrupt

requests by setting the error interrupt enable bit (ERRIE). See 20.8 Interrupts.

20.10.2 Stop Mode

The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not

affect register conditions. SPI operation resumes after an external interrupt. If stop mode is exited by

reset, any transfer in progress is aborted, and the SPI is reset.

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