AMD-K6-2ESLASH233AMZ datasheet(118/332 Pages) AMD

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Signal Descriptions

Chapter 5

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

5.19

DP[7:0] (Data Parity)

Pin Attribute

Bidirectional

Pin Location

See “Pin Designations by Functional Grouping” on page 301.

Summary

DP[7:0] are even parity bits for each valid byte of data — as

defined by BE[7:0]# —driven and sampled on the D[63:0] data

bus. Even parity means that the total number of odd (1) bits

within each byte of data and its respective data parity bit is an

even number. DP[7:0] are driven by the processor during write

cycles and sampled by the processor during read cycles.

If the processor detects bad parity on any valid byte of data

during a read cycle, PCHK# is asserted for one clock beginning

the clock edge after BRDY # is sampled asserted. The processor

does not take an internal exception as the result of detecting a

data parity check, and system logic must respond appropriately

to the assertion of this signal.

The eight data parity bits correspond to the eight bytes of the

data bus as follows:

For systems that do not support data parity, DP[7:0] should be

connected to VCC3 through pullup resistors.

Driven, Sampled, and

Floated

As Outputs: For single-transfer write cycles, the processor drives

DP[7:0] with valid parity one clock edge after the clock edge on

which ADS# is asserted and DP[7:0] remain in the same state

until the clock edge on which BRDY# is sampled asserted. If the

cycle is a writeback, DP[7:0] are driven one clock edge after the

clock edge on which ADS# is asserted and are subsequently

changed off the clock edge on which each BRDY# assertion of

the burst cycle is sampled.

As Inputs: During read cycles, the processor samples DP[7:0] on

the clock edge on which BRDY# is sampled asserted.

DP7: D[63:56]

DP3: D[31:24]

DP6: D[55:48]

DP2: D[23:16]

DP5: D[47:40]

DP1: D[15:8]

DP4: D[39:32]

DP0: D[7:0]

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