AMD-K6-2ESLASH233AMZ datasheet(114/332 Pages) AMD

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Signal Descriptions

Chapter 5

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

5.13

BRDYC# (Burst Ready Copy)

Pin Attribute

Input, Internal Pullup

Pin Location

Y-03

Summary

BRDYC # has the identical function as BRDY #. In the event

BRDY # becomes too heavily loaded due to a large fanout or

loading in a system, BRDYC # can be used to reduce this

loading, which improves timing.

Sampled

BRDYC# is sampled every clock edge within a bus cycle starting

with the clock edge after the clock edge that negates ADS#.

5.14

BREQ (Bus Request)

Pin Attribute

Output

Pin Location

AJ-01

Summary

BREQ is asserted by the processor to request the bus in order to

complete an internally pending bus cycle. The system logic can

use BREQ to arbitrate among the bus participants. If the

processor does not own the bus, BREQ is asserted until the

processor gains access to the bus in order to begin the pending

cycle or until the processor no longer needs to run the pending

cycle. If the processor currently owns the bus, BREQ is asserted

with ADS #. The processor asserts BREQ for each assertion of

ADS# but does not necessarily assert ADS# for each assertion of

BREQ.

Driven

BREQ is asserted off the same clock edge on which ADS # is

asserted. BREQ can also be asserted off any clock edge,

independent of the assertion of ADS #. BREQ can be negated

one clock edge after it is asserted.

The processor always drives BREQ except in the three-state test

mode.

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