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AMD-K6-2E/233AMZ bảng dữ liệu(PDF) 261 Page - Advanced Micro Devices |
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AMD-K6-2E/233AMZ bảng dữ liệu(HTML) 261 Page - Advanced Micro Devices |
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261 / 332 page ![]() Chapter 12 Test and Debug 243 22529B/0—January 2000 AMD-K6™-2E Processor Data Sheet Preliminary Information Figure 86. Debug Registers DR3, DR2, DR1, and DR0 DR3–DR0. The processor allows the setting of up to four breakpoints. DR3–DR0 contain the linear addresses for breakpoint 3 through breakpoint 0, respectively, and are compared to the linear addresses of processor cycles to determine if a breakpoint occurs. Debug register DR7 defines the specific type of cycle that must occur in order for the breakpoint to occur. DR5–DR4. When debugging extensions are disabled (bit 3 of CR4 is 0), the DR5 and DR4 registers are mapped to DR7 and DR6, respectively, in order to be software compatible with previous generations of x86 processors. When debugging extensions are 9 8765 432 10 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 Breakpoint 3 32-bit Linear Address DR3 9 8765 432 10 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 Breakpoint 0 32-bit Linear Address DR0 9 8765 432 10 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 Breakpoint 2 32-bit Linear Address DR2 9 876 5432 10 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 Breakpoint 1 32-bit Linear Address DR1 |
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