AMD-K6-2ESLASH233AMZ datasheet(245/332 Pages) AMD

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Chapter 12

Test and Debug

227

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

Test and Debug

The AMD-K6-2E processor implements various test and debug

modes to enable the functional and manufacturing testing of

systems and boards that use the processor. In addition, the

debug features of the processor allow designers to debug the

instruction execution of software components. This chapter

describes the following test and debug features:

Built-In Self-Test (BIST)—The BIST, which is invoked after

the falling transition of RESET, runs internal tests that

exercise most on-chip RAM structures.

Three-State Test Mode—A test mode that causes the

processor to float its output and bidirectional pins.

Boundary-Scan Test Access Port (TAP) —The Joint Test

Action Group (JTAG) test access function defined by the

IEEE

Standard

Test

Access

Port

and

Boundary-Scan

Architecture (IEEE 1149.1-1990) specification.

Level-One (L1) Cache Inhibit—A feature that disables the

processor’s internal L1 instruction and data caches.

Debug Support —Consists of all x86-compatible software

debug features, including the debug extensions.

12.1

Built-In Self-Test (BIST)

Following the falling transition of RESET, the processor

unconditionally runs its built-in self test (BIST). The internal

resources tested during BIST include the following:

L1 instruction and data caches

Instruction and Data Translation Lookaside Buffers (TLBs)

The contents of the EAX general-purpose register after the

completion of reset indicate if the BIST was successful.

If EAX contains 0000_0000h, then BIST was successful.

If EAX is non-zero, the BIST failed.

Following the completion of the BIST, the processor jumps to

address FFFF_FFF0h to start instruction execution, regardless

of the outcome of the BIST. The BIST takes approximately

295,000 processor clocks to complete.

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