AMD-K6-2ESLASH233AMZ datasheet(158/332 Pages) AMD

158 / 332 page

140

Bus Cycles

Chapter 6

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

Misaligned

Single-Transfer

Memory Read and

Write

Figure 53 on page 141 shows a misaligned (split) memory read

followed by a misaligned memory write. Any cycle that is not

aligned as defined in “SCYC (Split Cycle)” on page 120 is

considered misaligned. When the processor encounters a

misaligned access, it determines the appropriate pair of bus

cycles — each with its own ADS# and BRDY# — required to

complete the access.

The AMD-K6-2E processor performs misaligned memory reads

and memory writes using least-significant bytes (LSBs) first

followed by most-significant bytes (MSBs). Table 24 shows the

order. In the first memory read cycle in Figure 53, the processor

reads the least-significant bytes. Immediately after the

processor samples BRDY# asserted, it drives the second bus

cycle to read the most-significant bytes to complete the

misaligned transfer.

Similarly, the misaligned memory write cycle in Figure 53

transfers the LSBs to the memory bus first. In the next cycle,

after the processor samples BRDY# asserted, the MSBs are

written to the memory bus.

Table 24. Bus-Cycle Order During Misaligned Memory Transfers

Type of Access

First Cycle

Second Cycle

Memory Read

LSBs

MSBs

Memory Write

LSBs

MSBs

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