AMD-K6-2ESLASH233AMZ datasheet(148/332 Pages) AMD

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Signal Descriptions

Chapter 5

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

5.55

Pin Tables by Type

Table 18. Input Pin Types

Name

Type

Name

Type

A20M#1

Notes:

1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup

and hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.

Asynchronous

IGNNE#1

Asynchronous

AHOLD

Synchronous

INIT2

2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup

and hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and

must remain asserted at least two clocks.

Asynchronous

BF[2:0]3

3. BF[2:0] are sampled during the falling transition of RESET. They must meet a minimum setup time of 1.0 ms and a minimum

hold time of two clocks relative to the negation of RESET.

Synchronous

INTR1

Asynchronous

BOFF#

Synchronous

INV

Synchronous

BRDY#

Synchronous

KEN#

Synchronous

BRDYC#

Synchronous

NA#

Synchronous

CLK

Clock

NMI2

Asynchronous

EADS#

Synchronous

RESET4,5

4. During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and VCC

reach specification before it is negated.

5. During a warm reset, while CLK and VCC are within their specification, RESET must remain asserted for a minimum of 15 clocks

prior to its negation.

Asynchronous

EWBE#6

6. When EFER[3] is 1, EWBE# is ignored by the processor.

Synchronous

SMI#2

Asynchronous

FLUSH#2,7

7. FLUSH# is also sampled during the falling transition of RESET and can be asserted synchronously or asynchronously. To be

sampled on a specific clock edge, setup and hold times must be met relative to the clock edge before the clock edge on which

RESET is sampled negated. If asserted asynchronously, FLUSH# must meet a minimum setup and hold time of two clocks

relative to the negation of RESET.

Asynchronous

STPCLK#1

Asynchronous

HOLD

Synchronous

WB/WT#

Synchronous

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