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ADC3683 bảng dữ liệu(PDF) 24 Page - Texas Instruments

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tên linh kiện ADC3683
Giải thích chi tiết về linh kiện  ADC3683-SP Space Grade 18-Bit 1 to 65MSPS, Low Noise, Ultra-low Power Dual Channel ADC
PDF  70 Pages
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Trang chủ  http://www.ti.com
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ADC3683 bảng dữ liệu(HTML) 24 Page - Texas Instruments

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7.3.4 Digital Down Converter
The ADC3683-SP includes an optional on-chip digital down conversion (DDC) decimation filter that can be
enabled via SPI register settings. Supporting complex decimation by 2, 4, 8, 16 and 32 using a digital mixer and
a 32-bit numerically controlled oscillator (NCO) as shown in Figure 7-17.
Supporting a mode with real decimation where the complex mixer is bypassed (NCO is set to 0 for lowest power
consumption) and the digital filter acts as a low pass filter.
Internally, the decimation filter calculations are performed with a 20-bit resolution to avoid any SNR degradation
due to quantization noise limitation. The Output Formatter truncates to the selected resolution prior to outputting
the data on the digital interface.
ADC
Filter
I
SYNC
NCO
32bit
Digital
Interface
I
N
Q
Q
Figure 7-17. Internal Digital Decimation Filter
7.3.4.1 DDC MUX
The ADC3683-SP contains a MUX in front of the digital decimation filter which allows ADC ChA to be connected
to DDC ChB. This feature is enabled and controlled using the SPI interface. Subsequently the output interface
corresponds to the DDC channel A and B.
ADC
N
Digital Downconverter
NCO
ADC
N
NCO
DDC MUX
Figure 7-18. DDC MUX
ADC3683-SP
SBASAB5 – MARCH 2024
www.ti.com
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Product Folder Links: ADC3683-SP



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