ADC3683 datasheet(15/70 Pages) TI1

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7 Detailed Description

7.1 Overview

The ADC3683-SP is a low noise, ultra-low power 18-bit high-speed dual channel ADC family supporting

sampling rates up to 65MSPS. It offers DC precision together with IF sampling support which makes it designed

for a wide range of applications. The device is equipped with an internal reference option, but it also supports the

use of an external, high precision 1.6V reference or an external 1.2V reference which is buffered and gained up

internally. Because of the inherent low latency architecture, the digital output result is available after only one or

two clock cycles depending on the digital output interface.

An optional programmable digital down converter enables external anti-alias filter relaxation as well as output

data rate reduction. The digital filter provides a 32-bit programmable NCO and supports both real or complex

decimation.

The ADC3683-SP uses a serial LVDS (SLVDS) interface to output the data which minimizes the number of

digital interconnects. The device supports a two-lane (2-wire), a one-lane (1-wire) and a half-lane (1/2-wire)

option. The device includes a digital output formatter which supports output resolutions from 14 to 20-bit.

The device features and control options can be set up either through pin configurations or via SPI register writes.

7.2 Functional Block Diagram

Control

AIN

CLK

VREF

ADC

18bit

1.2V REF

REFBUF

Digital Downconverter

NCO

BIN

ADC

18bit

NCO

0.95V

VCM

DB0/1

DCLKIN

DCLK

FCLK

DA0/1

Dig I/F

SLVDS

Crosspoint

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ADC3683-SP

SBASAB5 – MARCH 2024

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