ADC3683 datasheet(20/70 Pages) TI1

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7.3.2 Clock Input

To maximize the ADC SNR performance, the external sampling clock should be low jitter and differential

signaling with a high slew rate. This is especially important in IF sampling applications (Figure 7-10 and Figure

7-11). For less jitter sensitive applications, the device provides the option to operate with single ended signaling

which saves additional power consumption.

Figure 7-10. AC Performance vs Clock Amplitude

(Differential Clock Input)

Figure 7-11. AC Performance vs Clock Amplitude

(Single Ended Clock Input)

7.3.2.1 Single Ended vs Differential Clock Input

The ADC3683-SP can be operated using a differential or a single ended clock input where the single ended

clock consumes less power consumption. However, clock amplitude impacts the ADC aperture jitter and

consequently the SNR. For maximum SNR performance, a large clock signal with fast slew rates needs to

be provided.

• Differential Clock Input: The clock input can be AC coupled externally. The ADC3683-SP provides internal

bias.

• Single Ended Clock Input: This mode needs to be configured using SPI register (0x0E, D2 and D0), or with

the REFBUF pin. In this mode, there is no internal clock biasing, so the clock input needs to be DC coupled

around a 0.9V center. The unused input needs to be AC coupled to ground.

VCM

0.9V

CLKP

CLKM

5kO

CLKP

CLKM

0.9V

1.8V

Figure 7-12. External and internal connection using differential (left) and single ended (right) clock input

ADC3683-SP

SBASAB5 – MARCH 2024

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