IMX7DCEC datasheet(116/161 Pages) NXP

tên linh kiện	IMX7DCEC

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Electrical characteristics

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

116

NOTE

HSIC is DDR signal, following timing spec is for both rising and falling

edge.

4.10.15.1 Transmit timing

Figure 85. USB HSIC transmit waveform

4.10.15.2 Receive timing

Figure 86. USB HSIC receive waveform

Table 91. USB HSIC transmit parameters

Name

Parameter

Min

Max

Unit

Comment

Tstrobe

strobe period

4.165

4.169

Todelay

data output delay time

550

1350

Measured at 50% point

Tslew

strobe/data rising/falling time

0.7

V/ns

Averaged from 30% – 70% points

Table 92. USB HSIC receive parameters1

1 The timings in the table are guaranteed when:

—AC I/O voltage is between 0.9x to 1x of the I/O supply

—DDR_SEL configuration bits of the I/O are set to (10)b

Name

Parameter

Min

Max

Unit

Comment

Tstrobe

strobe period

4.165

4.169

Thold

data hold time

300

Measured at 50% point

Tsetup

data setup time

365

Measured at 50% point

Tslew

strobe/data rising/falling time

0.7

V/ns

Averaged from 30% – 70% points

USB_H_STROBE

USB_H_DATA

Todelay

Tstrobe

Todelay

USB_H_STROBE

USB_H_DATA

Thold

Tstrobe

Tsetup

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