IMX7DCEC datasheet(73/161 Pages) NXP

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Electrical characteristics

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

Figure 32 shows the LPDDR2 read timing diagram. The timing parameters for this diagram appear in

Table 55.

Figure 32. LPDDR2 read cycle

1 To receive the reported setup and hold values, read calibration should be performed in order to locate the DRAM_SDQSx_P

in the middle of DRAM_DATA_xx window.

2 All measurements are in reference to Vref level.

3 Measurements were done using balanced load and 25  resistor from outputs to DDR_VREF.

4.9

General-purpose media interface (GPMI) timing

The i.MX 7Dual GPMI controller is a flexible interface NAND Flash controller with 8-bit data width, up

to 200 MB/s I/O speed and individual chip select.

It supports Asynchronous Timing mode, Source Synchronous Timing mode and Toggle Timing mode

separately, as described in the following subsections.

4.9.1

Asynchronous mode AC timing (ONFI 1.0 compatible)

Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The

maximum I/O speed of GPMI in asynchronous mode is about 50 MB/s. Figure 33 through Figure 36

depicts the relative timing between GPMI signals at the module level for different operations under

asynchronous mode. Table 56 describes the timing parameters (NF1–NF17) that are shown in the figures.

Table 55. LPDDR2 read cycle

Parameter

Symbol

CK = 533 MHz

Unit

Min

Max

LP26

Minimum required DRAM_DATAxx valid window width for LPDDR2

—

230

—

DRAM_SDCLKx_P

DRAM_SDCLKx_N

DRAM_SDQSx_P

DRAM_DATAxx

DATA

LP26

(input)

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